Revision History
Package Dimensions
MM912F634
Freescale Semiconductor
338
6
Revision History
.
Revision
Date
Description
1.0
05/2010
Initial release.
2.0
7/2010
MM912F634Cxxxx (Revision C) Introduced
MM912F634Cxxxx (Revision C) Lx Input Threshold / Hysteresis Limit added. See Table 23,
Static Electrical Characteristics - High Voltage Inputs - Lx
VDDXSTOP minimum value deleted. See Table 17, Static Electrical Characteristics - Voltage
Regulator 5.0 V (VDDX)
IVDDLIMXSTOP ratings changed. See Table 17, Static Electrical Characteristics - Voltage
Regulator 5.0 V (VDDX)
IVDDLIMRUN minimum value deleted for all values of TJ. See Table 18, Static Electrical
Characteristics - Voltage Regulator 2.5 V (VDD)
IVDDLIMSTOP minimum value deleted. See Table 18, Static Electrical Characteristics -
Voltage Regulator 2.5 V (VDD)
TSg typical value changed to 9.17 mV/k. See Table 27, Static Electrical Characteristics -
Temperature Sensor - TSENSE
Deleted devices MM912F634BC1AE, MM912F634BV2AE, MM912F634BC2AE,
MM912F634BV3AE, MM912F634BC3AE, MM912F634CC1AE, MM912F634CC2AE,
MM912F634CV3AE, MM912F634CC3AE from Table 1, Ordering Information, as well as
references to these devices in sections 3.5, 3.6 & 3.7
Deleted "Data Flash" column in Table 1, Ordering Information, since this feature is not
available for the MM912F634
Deleted all references to Analog Options "A3" & "A4" in Section 4.1.3, Analog Die Options
Changed Analog Option designations from "A1" & "A2" to "1" & "2", respectively, in Table 1,
Ordering Information, and Table 2, Analog Options
Clarified instructions on use of unused pins in devices with Analog Option "2"
Changed MM912F634Cxxxx Lx High Detection Threshold VTHH (min) from 2.7 V to 2.6 V for
the range 7.0 V ≤ VSUP ≤ 27 V. Changed max & typical Hysteresis VHYS for
MM912F634Cxxxx. Applied these new values to the full range of 5.5 V ≤ VSUP ≤ 27 V. See
Table 19, Static Electrical Characteristics - High Voltage Inputs – Lx
Added separate HBM ESD rating (VHBM) for HSx pins of +/-3000V. See Table 46, ESD and
Latch-up Protection Characteristics
3.0
10/2010
Added MM912F634CV2AP to the ordering information
Updated to standard form and style
Added the 98ASA00173D (48-PIN LQFP) package drawing to the Packaging section
Added symbol fBUSMAX to Max. Bus Frequency (MHz) column in Table 1.
Replaced all references to 20 MHz bus frequency with fBUSMAX, and added a note referring
to Table 1. See Table 8 – Operating Conditions, Table 9 – Supply Currents, Table 28 –
Dynamic Electrical Characteristics – Die to Die Interface – D2D.
Added reference to 16 MHz maximum CPU Bus Frequency for MM1912F634CV2AP to
section 4.25.1.1 (MM912F634 – MCU Die Overview: Features)
Changed Baud Rate data to reflect a 20 MHz Bus Clock in Table 409 – Example SPI Baud
Rate Selection.
4.0
10/2010
Removed part number MM912F634BV1AE from data sheet.
5.0
11/2010
Corrected several typos throughout the document - No technical changes
6.0
9/2012
Added MM912F634DV1AE, MM912F634DV2AE, MM912F634DV2AP to the ordering
information.
Redefined RθJA for both LQFP packages.
7.0
5/2013
LQFP48 to add JEDEC board information.