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參數(shù)資料
| 型號(hào)： | KIT912F634EVME |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 155/339頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL FOR MM912F634 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | MCU |
| 適用于相關(guān)產(chǎn)品： | MM912F634 |
| 所含物品： | 板，線(xiàn)纜，CD |
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Functional Description and Application Information
S12S Debug (S12SDBGV1) Module
MM912F634
Freescale Semiconductor
238
4.31.4.5.3.1
Loop1 Mode
NOTE
In certain very tight loops, the source address will have already been fetched again before
the background comparator is updated. This results in the source address being stored twice
before further duplicate entries are suppressed. This condition occurs with branch-on-bit
instructions when the branch is fetched by the first P-cycle of the branch or with
loop-construct instructions in which the branch is fetched with the first or second P cycle.
See examples below:
Loop1 mode, similarly to Normal mode also stores only COF address information to the trace buffer, it however allows the filtering
out of redundant information.
The intent of Loop1 mode is to prevent the Trace Buffer from being filled entirely with duplicate information from a looping
construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after
address information is placed in the Trace Buffer, the DBG module writes this value into a background register. This prevents
consecutive duplicate address entries in the Trace Buffer resulting from repeated branches.
Loop1 mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping
constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these
would most likely indicate a bug in the user’s code that the DBG module is designed to help find.
LOOP
INX
; 1-byte instruction fetched by 1st P-cycle of BRCLR
BRCLR
CMPTMP,#$0c,LOOP ; the BRCLR instruction also will be fetched by 1st
; P-cycle of BRCLR
LOOP2
BRN
*
; 2-byte instruction fetched by 1st P-cycle of DBNE
NOP
; 1-byte instruction fetched by 2nd P-cycle of DBNE
DBNE
A,LOOP2
; this instruction also fetched by 2nd P-cycle of DBNE
4.31.4.5.3.2
Detail Mode
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This mode is intended to
supply additional information on indexed, indirect addressing modes, where storing only the destination address would not
provide all information required for a user to determine where the code is in error. This mode also features information bit storage
to the trace buffer, for each address byte storage. The information bits indicates the size of access (word or byte) and the type
of access (read or write).
When tracing in Detail mode, all cycles are traced except those when the CPU is either in a free or opcode fetch cycle.
4.31.4.5.3.3
Pure PC Mode
NOTE:
When tracing is terminated using forced breakpoints, latency in breakpoint generation
means that opcodes following the opcode causing the breakpoint can be stored to the trace
buffer. The number of opcodes is dependent on program flow. This should be avoided by
using tagged breakpoints.
In Pure PC mode, tracing from the CPU the PC addresses of all executed opcodes, including illegal opcodes are stored.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| KIT912H634EVME | 功能描述:開(kāi)發(fā)板和工具包 - S08 / S12 DUAL LOW&HIDE SWITCH EVB RoHS:否 產(chǎn)品:Development Kits 工具用于評(píng)估:MC9S12G128 核心:S12 接口類(lèi)型:CAN, LIN, RS-232, USB 工作電源電壓:5 V 制造商:Freescale Semiconductor |
| KIT912J637EVME | 功能描述:電源管理IC開(kāi)發(fā)工具 BATTERY SENSOR 912J637 RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類(lèi)型:Battery Management 工具用于評(píng)估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| KIT912S812ECUEVM | 功能描述:電源管理IC開(kāi)發(fā)工具 Single Cylinder S12XS E RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類(lèi)型:Battery Management 工具用于評(píng)估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| Kit-916 | 制造商:ANDERSON POWER PRODUCTS 功能描述:KIT |
| Kit-917 | 制造商:ANDERSON POWER PRODUCTS 功能描述:KIT |
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