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參數(shù)資料
| 型號： | KFN2G16Q2M-DED6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | MuxOneNAND FLASH MEMORY |
| 中文描述： | MuxOneNAND閃存 |
| 文件頁數(shù)： | 94/124頁 |
| 文件大?。?/td> | 1550K |
| 代理商： | KFN2G16Q2M-DED6 |
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MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
FLASH MEMORY
94
The MuxOneNAND device has DQ6 Toggle bit. Toggle bit is another option to detect whether an internal load operation is in progress
or completed. Once the BufferRAM(BootRAM, DataRAM0, DataRAM1) is at a busy state during internal load operation, DQ6 will tog-
gle. Toggling DQ6 will stop after the device completes its internal load operation. The MuxOneNAND device’s DQ6 Toggle will be
valid only when host reads BufferRAM designated by BSA which will be loaded by internal load operation. DQ6 toggle can be used
350ns after load command(0000h, 0013h, and 00E0h of Command based Operation) issue, until data sensing from the NAND Flash
Array memory into Page Buffer and transferring from the Page Buffer to the DataRAM are finished. By reading the same address
more than twice utilizing either asynchronous or synchronous read (Figure 6.14, 6.15 and 6.16), the host will read toggled value of
DQ6 and the rest of DQ’s are not guaranteed to be fixed value. DQ6 toggle is only for reading status of BufferRAM which is being
loaded by internal operation, that is, BufferRAM designated by BSA. Host may read previous data from BufferRAM not pointed by
BSA during internal load operation.
DQ6 toggle bit can be useful at Cold Reset to determine the ready/busy state of MuxOneNAND. Since INT pin is initially at High-Z
state, when host needs to check the completion of bootcode copy operation, the host cannot judge the ready/busy status of Mux-
OneNAND by INT pin. Therefore, by checking DQ6 toggle of BootRAM, the host should detect the completion of bootcode copy.
Status
DQ15~DQ7
DQ6
DQ5~DQ0
In Progress
Data Loading
X (Don’t Care)
Toggle
X (Don’t Care)
3.13 DQ6 Toggle Bit
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