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參數(shù)資料
| 型號： | KFN2G16Q2M-DED6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | MuxOneNAND FLASH MEMORY |
| 中文描述： | MuxOneNAND閃存 |
| 文件頁數(shù)： | 73/124頁 |
| 文件大?。?/td> | 1550K |
| 代理商： | KFN2G16Q2M-DED6 |
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MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
FLASH MEMORY
73
First Clock Cycle
The initial word is output at tIAA after the rising edge of the first CLK cycle. The RDY output indicates the initial word is ready to the
system by pulsing high. If the device is accessed synchronously while it is set to Asynchronous Read Mode, the first data can still be
read out.
Subsequent Clock Cycles
Subsequent words are output (Burst Access Time from Valid Clock to Output) tBA after the rising edge of each successive clock
cycle, which automatically increments the internal address counter.
Terminating Burst Read
The device will continue to output sequential burst data until the system asserts /CE high, or /RP low, wrapping around until it reaches
the designated address (see Section 2.7.3 for address map information). Alternately, a Cold/Warm/Hot Reset, or a /WE low pulse will
terminate the burst read operation.
Synchronous Read Boundary
Division
Add.map(word order)
BootRAM Main(0.5Kw)
0000h~01FFh
BrfferRAM0 Main(1Kw)
0200h~05FFh
BufferRAM1 Main(1Kw)
0600h~09FFh
Reserved Main
0A00h~7FFFh
BootRAM Spare(16w)
8000H~800Fh
BufferRAM0 Spare(32w)
8010h~802Fh
BufferRAM1 Spare(32w)
8030h~804Fh
Reserved Spare
8050h~8FFFh
Reserved Register
9000h~EFFFh
Register(4Kw)
F000h~FFFFh
Not Support
Not Support
* Reserved area is not available on Synchronous read
3.7.2.2 4-, 8-, 16-, 32-Word Linear Burst Read Operation
See Timing Diagram 6.1
An alternate Burst Read Mode enables a fixed number of words to be read from consecutive address.
The device supports a burst read from consecutive addresses of 4-, 8-, 16-, and 32-words with a linear-wrap around. When the last
word in the burst has been reached, assert /CE and /OE high to terminate the operation.
In this mode, the start address for the burst read can be any address of the address map with one exception. The device does not
support a 32-word linear burst read on the spare area of the BufferRAM.
Not Support
Not Support
Not Support
3.7.2.1 Continuous Linear Burst Read Operation
See Timing Diagram 6.2
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