OneNAND512/OneNAND1GDDP
FLASH MEMORY
6
1. FEATURES
Design Technology: 0.12um
Voltage Supply
- 1.8V device(KFG1216Q2M) : 1.7V~1.95V
- 2.65V device(KFG1216D2M) : 2.4V~2.9V
- 3.3V device(KFG1216U2M) : 2.7V~3.6V
Organization
- Host Interface:16bit
Internal BufferRAM(5K Bytes)
- 1KB for BootRAM, 4KB for DataRAM
NAND Array
- Page Size : (2K+64)bytes
- Block Size : (128K+4K)bytes
Architecture
Host Interface type
- Synchronous Burst Read
: Clock Frequency: up to 54MHz
: Linear Burst - 4, 8, 16, 32 words with wrap-around
: Continuous Sequential Burst(1K words)
- Asynchronous Random Read
: Access time of 76ns
- Asynchronous Random Write
Programmable Read latency
Multiple Sector Read
- Read multiple sectors by Sector Count Register(up to 4 sectors)
Reset Mode
- Cold Reset / Warm Reset / Hot Reset / NAND Flash Reset
Power dissipation (typical values)
- Standby current : 10uA@1.8V, 20uA@2.65V/3.3V for single, 20uA@1.8V, 40uA@2.65V/3.3V for DDP
- Synchronous Burst Read current(54MHz) : 12mA@1.8V device, 20mA@2.65V/3.3V device
- Load current : 20mA@1.8V device, 25mA@2.65V/3.3V device
- Program current: 20mA@1.8V device, 25mA@2.65V/3.3V device
- Erase current: 15mA@1.8V device, 20mA@2.65V/3.3V device
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
Performance
Voltage detector generating internal reset signal from Vcc
Hardware reset input (RP)
Data Protection
- Write Protection for BootRAM
- Write Protection mode for NAND Flash Array
- Write protection during power-up
- Write protection during power-down
User-controlled One Time Programmable(OTP) area
Internal 2bit EDC / 1bit ECC
Internal Bootloader supports Booting Solution in system
Hardware Features
Handshaking Feature
- INT pin: Indicates Ready / Busy of OneNAND
- Polling method: Provides a software method of detecting the Ready / Busy status of OneNAND
Detailed chip information by ID register
Software Features
Package
- 63ball, 9.5mm x 12mm x max 1.0mmt , 0.8mm ball pitch FBGA
Packaging