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參數(shù)資料
| 型號(hào)： | ITF86130SK8T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 功率晶體管 |
| 英文描述： | N-Channel, Logic Level, Power MOSFET(N溝道邏輯電平功率MOS場(chǎng)效應(yīng)管) |
| 中文描述： | 14 A, 30 V, 0.012 ohm, N-CHANNEL, Si, POWER, MOSFET, MS-012AA |
| 封裝： | PLASTIC, SO-8 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 174K |
| 代理商： | ITF86130SK8T |
6
Thermal Resistance vs. Mounting Pad
Area
The maximum rated junction temperature, T
JM
, and the
thermal resistance of the heat dissipating path determines the
maximum allowable device power dissipation, P
DM
, in an
application. Therefore the application’s ambient temperature,
T
A
(
o
C), and thermal resistance R
θ
JA
(
o
C/W) must be reviewed
to ensure that T
JM
is never exceeded. Equation 1
mathematically represents the relationship and serves as the
basis for establishing the rating of the part.
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
DM
is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. Thenumberofcopperlayersandthethicknessoftheboard.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the
R
θ
JA
for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
Test Circuits and Waveforms
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
V
DD
Q
g(TH)
Q
gs
V
GS
= 1V
Q
g(5)
V
GS
= 5V
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
g(REF)
0
0
Q
gd
V
GS
0V
R
GS
R
L
DUT
+
-
V
GS
V
DS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
(EQ. 1)
PDM
θ
JA
–
------------------------------
)
=
ITF86130SK8T
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