參數(shù)資料
型號(hào)： ISP1562BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus PCI Host Controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁(yè)數(shù)： 76/98頁(yè)
文件大?。?/td> 442K
代理商： ISP1562BE
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
76 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
19 to 16 PTC[3:0]
Port Test Control
: Default = 0000b. When this field is logic 0, the port is
not operating in test mode. A nonzero value indicates that it is operating in
test mode and test mode is indicated by the value. The encoding of the test
mode bits are:
0000b —
Test mode disabled
0001b —
Test J_STATE
0010b —
Test K_STATE
0011b —
Test SE0_NAK
0100b —
Test packet
0101b —
Test FORCE_ENABLE
0110b to 1111b —
reserved.
-
Port Owner
: Default = 1. This bit unconditionally goes to logic 0 when CF
(bit 0) in the CONFIGFLAG register makes logic 0 to logic 1 transition. This
bit unconditionally goes to logic 1 when the CF bit is logic 0. The system
software uses this field to release ownership of the port to a selected Host
Controller, if the attached device is not a high-speed device. Software writes
logic 1 to this bit, if the attached device is not a high-speed device. Logic 1
in this bit means that a companion Host Controller owns and controls the
port.
Port Power
: The function of this bit depends on the value of PPC (bit 4) in
the HCSPARAMS register.
If PPC = 0 and PP = 1 —
The Host Controller does not have port power
control switches. Always powered.
If PPC = 1 and PP = 1 or 0 —
The Host Controller has port power control
switches. This bit represents the current setting of the switch: logic 0 = off,
logic 1 = on. When PP is logic 0, the port is nonfunctional and will not report
any status.
When an overcurrent condition is detected on a powered port and PPC is
logic 1, the PP bit in each affected port may be changed by the Host
Controller from logic 1 to logic 0, removing power from the port.
Line Status
: This field reflects the current logical levels of the DP (bit 11)
and DM (bit 10) signal lines. These bits are used to detect low-speed USB
devices before the port reset and enable sequence. This field is valid only
when the Port Enable bit is logic 0, and the Current Connect Status bit is set
to logic 1.
00b —
SE0: Not a low-speed device, perform EHCI reset
01b —
K-state: Low-speed device, release ownership of port
10b —
J-state: Not a low-speed device, perform EHCI reset
11b —
Undefined: Not a low-speed device, perform EHCI reset.
If the PP bit is logic 0, this field is undefined.
-
15 to 14 reserved
13
PO
12
PP
11 to 10 LS[1:0]
9
reserved
Table 107: PORTSC 1, 2 - Port Status and Control 1, 2 register bit description
…continued
Address: Value read from func2 of address 10h + 64h + (4 x Port Number
1) where Port Number
is 1, 2
Bit
Symbol
Description
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