參數(shù)資料
型號(hào)： ISP1562BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus PCI Host Controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù)： 41/98頁
文件大?。?/td> 442K
代理商： ISP1562BE
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
41 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
11.1.5
HcInterruptEnable register
Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control
which events generate a hardware interrupt. A hardware interrupt is requested on the host
bus if the following conditions occur:
A bit is set in the HcInterruptStatus register.
The corresponding bit in the HcInterruptEnable register is set.
The MIE (MasterInterruptEnable) bit is set.
Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing logic 0 to
a bit in this register leaves the corresponding bit unchanged. On a read, the current value
of this register is returned. The bit allocation is given in
Table 50
.
[1]
The reserved bits should always be written with the reset value.
Table 50:
Address: Value read from func0 or func1 of address 10h + 10h
Bit
31
Symbol
MIE
Reset
0
Access
R/W
Bit
23
Symbol
Reset
0
Access
R/W
Bit
15
Symbol
Reset
0
Access
R/W
Bit
7
Symbol
reserved
[1]
RHSC
Reset
0
Access
R/W
HcInterruptEnable - Host Controller Interrupt Enable register bit allocation
30
OC
0
R/W
22
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
0
0
0
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
0
0
0
0
0
0
0
R/W
6
R/W
5
FNO
0
R/W
R/W
4
UE
0
R/W
R/W
3
RD
0
R/W
R/W
2
SF
0
R/W
R/W
1
WDH
0
R/W
R/W
0
SO
0
R/W
0
R/W
Table 51:
Address: Value read from func0 or func1 of address 10h + 10h
Bit
Symbol
Description
31
MIE
Master Interrupt Enable
:
0 —
Ignore
1 —
Enables interrupt generation by events specified in other bits of this
register.
30
OC
Ownership Change
:
0 —
Ignore
1 —
Enables interrupt generation because of Ownership Change.
29 to 7
reserved
-
HcInterruptEnable - Host Controller Interrupt Enable register bit description
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