參數(shù)資料
型號(hào)： ISP1562BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus PCI Host Controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁(yè)數(shù)： 40/98頁(yè)
文件大?。?/td> 442K
代理商： ISP1562BE
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
40 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
[1]
The reserved bits should always be written with the reset value.
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
23
22
21
20
19
18
17
16
reserved
[1]
0
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
0
0
0
0
0
0
0
0
R/W
7
R/W
6
RHSC
0
R/W
R/W
5
FNO
0
R/W
R/W
4
UE
0
R/W
R/W
3
RD
0
R/W
R/W
2
SF
0
R/W
R/W
1
WDH
0
R/W
R/W
0
SO
0
R/W
reserved
[1]
0
R/W
Table 49:
Address: Value read from func0 or func1 of address 10h + 0Ch
Bit
Symbol
Description
31
reserved
-
30
OC
OwnershipChange
: This bit is set by the Host Controller when HCD sets
OCR (bit 3) in the HcCommandStatus register. This event, when
unmasked, will always immediately generate a System Management
Interrupt (SMI). This bit is forced to logic 0 when the SMI# pin is not
implemented.
29 to 7
reserved
-
6
RHSC
RootHubStatusChange
: This bit is set when the content of HcRhStatus or
the content of any of HcRhPortStatus[NumberofDownstreamPort] has
changed.
5
FNO
FrameNumberOverflow
: This bit is set when the MSB of HcFmNumber
(bit 15) changes value, or after the HccaFrameNumber is updated.
4
UE
UnrecoverableError
: This bit is set when the Host Controller detects a
system error not related to USB. The Host Controller should not proceed
with any processing nor signaling before the system error is corrected. The
HCD clears this bit after the Host Controller is reset.
3
RD
ResumeDetected
: This bit is set when the Host Controller detects that a
device on the USB is asserting resume signaling. This bit is set by the
transition from no resume signaling to resume signaling. This bit is not set
when the HCD sets the USBRESUME state.
2
SF
Start-of-Frame
: At the start of each frame, this bit is set by the Host
Controller and an SOF token is generated at the same time.
1
WDH
WritebackDoneHead
: This bit is immediately set after the Host Controller
has written HcDoneHead to HccaDoneHead. Further, updates of
HccaDoneHead occur only after this bit is cleared. The HCD should only
clear this bit after it has saved the content of HccaDoneHead.
0
SO
SchedulingOverrun
: This bit is set when USB schedules for current frame
overruns and after the update of HccaFrameNumber. A scheduling overrun
increments the SOC[1:0] field (bits 17 to 16 of HcCommandStatus).
HcInterruptStatus - Host Controller Interrupt Status register bit description
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