參數(shù)資料
型號: ISP1562BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù): 25/98頁
文件大?。?/td> 442K
代理商: ISP1562BE
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
25 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
affect the actual operation of the EHCI Host Controller. The system-specific policy can be
established by BIOS initializing this register to a system-specific value. The system
software uses the information in this register when enabling devices and ports for remote
wake-up.
8.2.3
Power management registers
8.2.3.1
Cap_ID register
The Capability Identifier (Cap_ID) register when read by the system software as 01h
indicates that the data structure currently being pointed to is the PCI Power Management
data structure. Each function of a PCI device may have only one item in its capability list
with Cap_ID set to 01h. The bit description of the register is given in
Table 31
.
8.2.3.2
Next_Item_Ptr register
The Next Item Pointer (Next_Item_Ptr) register describes the location of the next item in
the function’s capability list. The value given is an offset into the function’s PCI
configuration space. If the function does not implement any other capabilities defined by
the PCI-SIG for inclusion in the capabilities list, or if power management is the last item in
the list, then this register must be set to 00h. See
Table 32
.
Table 29:
Legend: * reset value
Bit
Symbol
15 to 0
PORTWAKECAP
[15:0]
PORTWAKECAP - Port Wake Capability register (address 62h) bit description
Access
R/W
Value
0007h*
Description
Port Wake-Up Capability Mask
: EHCI
does not implement this feature.
Table 30:
Offset
Value read from address 34h + 0h
Value read from address 34h + 1h
Value read from address 34h + 2h
Value read from address 34h + 4h
Value read from address 34h + 6h
Power Management registers
Register
Capability Identifier (Cap_ID)
Next Item Pointer (Next_Item_Ptr)
Power Management Capabilities (PMC)
Power Management Control/Status (PMCSR)
Power Management Control/Status PCI-to-PCI Bridge
Support Extensions (PMCSR_BSE)
Data
Value read from address 34h + 7h
Table 31:
Address: Value read from address 34h + 0h
Legend: * reset value
Bit
Symbol
7 to 0
CAP_ID[7:0] R
Cap_ID - Capability Identifier register bit description
Access
Value
01h*
Description
ID
: This field when 01h identifies the linked list item as
being PCI Power Management registers.
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