參數(shù)資料
型號: ISP1562BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù): 28/98頁
文件大?。?/td> 442K
代理商: ISP1562BE
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
28 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
[1]
Sticky bit, if the function supports PME# from D3
cold
, then X is indeterminate at the time of initial operating system boot; X is 0 if the
function does not support PME# from D3
cold
.
The reserved bits should always be written with the reset value.
[2]
Table 35:
Address: Value read from address 34h + 4h
Bit
15
Symbol
PMES
Reset
X
[1]
Access
R/W
Bit
7
Symbol
Reset
0
Access
R/W
PMCSR - Power Management Control/Status register bit allocation
14
13
12
11
10
9
8
DS[1:0]
D_S[3:0]
PMEE
X
[1]
R/W
0
0
R
6
0
R
5
0
0
0
0
R/W
4
R/W
3
R/W
2
R/W
1
reserved
[2]
PS[1:0]
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 36:
Address: Value read from address 34h + 4h
Bit
Symbol
Description
15
PMES
PME Status
: This bit is set when the function normally asserts the PME#
signal independent of the state of the PMEE bit. Writing logic 1 to this bit
clears it and causes the function to stop asserting PME#, if enabled. Writing
logic 0 has no effect. This bit defaults to logic 0, if the function does not
support the PME# generation from D3
cold
. If the function supports the PME#
generation from D3
cold
, then this bit is sticky and must be explicitly cleared by
the operating system each time the operating system is initially loaded.
14 to 13 DS[1:0]
Data Scale
: This two-bit read-only field indicates the scaling factor when
interpreting the value of the Data register. The value and meaning of this field
vary, depending on which data value is selected by the D_S field. This field is
a required component of the Data register (offset 7) and must be
implemented, if the Data register is implemented. If the Data register is not
implemented, this field must return 00b when PMCSR is read.
12 to 9
D_S
[3:0]
Data register and the D_S field. This field is a required component of the
Data register (offset 7) and must be implemented, if the Data register is
implemented. If the Data register is not implemented, this field must return
00b when PMCSR is read.
PMCSR - Power Management Control/Status register bit description
Data_Select
: This four-bit field selects the data that is reported through the
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