參數(shù)資料
型號: ISP1562BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù): 35/98頁
文件大?。?/td> 442K
代理商: ISP1562BE
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
35 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
11.1.2
HcControl register
This register defines the operating modes for the Host Controller. All the fields in this
register, except for HCFS and RWC, are modified only by the HCD. The bit allocation is
given in
Table 44
.
[1]
The reserved bits should always be written with the reset value.
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
15
14
13
12
11
10
9
8
reserved
0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
REV[7:0]
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
Table 43:
Address: Value read from func0 or func1 of address 10h + 00h
Bit
Symbol
Description
31 to 8
reserved
-
7 to 0
REV[7:0]
Revision
: This read-only field contains the BCD representation of the
version of the HCI specification that is implemented by this Host
Controller. For example, a value of 11h corresponds to version 1.1. All
of the Host Controller implementations that are compliant with this
specification need to have a value of 10h.
HcRevision - Host Controller Revision register bit description
Table 44:
Address: Value read from func0 or func1 of address 10h + 04h
Bit
31
Symbol
Reset
0
Access
R/W
Bit
23
Symbol
Reset
0
Access
R/W
Bit
15
Symbol
Reset
0
Access
R/W
Bit
7
Symbol
HCFS[1:0]
Reset
0
Access
R/W
HcControl - Host Controller Control register bit allocation
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
0
0
0
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
RWE
0
R/W
2
PLE
0
R/W
R/W
9
RWC
0
R/W
1
R/W
8
IR
0
R/W
0
reserved
[1]
0
R/W
5
BLE
0
R/W
0
0
0
R/W
6
R/W
4
CLE
0
R/W
R/W
3
IE
0
R/W
CBSR[1:0]
0
0
0
R/W
R/W
R/W
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