參數(shù)資料
型號(hào)： ISP1562BE
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 總線(xiàn)控制器
英文描述： Hi-Speed Universal Serial Bus PCI Host Controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁(yè)數(shù)： 17/98頁(yè)
文件大?。?/td> 442K
代理商： ISP1562BE
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
17 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
8.2.1.4
Status register
The Status register is a 2 B read-only register used to record status information on PCI
bus-related events. For bit allocation, see
Table 8
.
2
BM
Bus Master
: Controls the ability of a device to act as a master on the PCI
bus.
0 —
Disables the device from generating PCI accesses. State after
RST# is logic 0.
1 —
Allows the device to behave as a bus master.
Memory Space
: Controls the response of a device to Memory Space
accesses.
0 —
Disables the device response. State after RST# is logic 0.
1 —
Allows the device to respond to memory space accesses.
IO Space
: Controls the response of a device to I/O space accesses.
0 —
Disables the device response. State after RST# is logic 0.
1 —
Allows the device to respond to I/O space accesses.
1
MS
0
IOS
Table 7:
Bit
Command register (address 04h) bit description
…continued
Symbol
Description
Table 8:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Status register (address 06h) bit allocation
15
14
DPE
SSE
0
0
R
R
7
6
FBBC
reserved
0
0
R
R
13
RMA
0
R
5
66MC
0
R
12
RTA
0
R
4
CL
1
R
11
STA
0
R
3
10
DEVSELT[1:0]
0
R
2
reserved
0
R
9
8
MDPE
0
R
0
1
R
1
0
R
0
R
0
R
Table 9:
Bit
15
Status register (address 06h) bit description
Symbol
Description
DPE
Detected Parity Error
: This bit must be set by the device whenever it
detects a parity error, even if the parity error handling is disabled.
SSE
Signaled System Error
: This bit must be set whenever the device asserts
SERR#. Devices that never assert SERR# do not need to implement this
bit.
RMA
Received Master Abort
: This bit must be set by a master device whenever
its transaction, except for Special Cycle, is terminated with Master-Abort. All
master devices must implement this bit.
RTA
Received Target Abort
: This bit must be set by a master device whenever
its transaction is terminated with Target-Abort. All master devices must
implement this bit.
STA
Signaled Target Abort
: This bit must be set by a target device whenever it
terminates a transaction with Target-Abort. Devices that never signal
Target-Abort do not need to implement this bit.
14
13
12
11
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ISP1562BE,518 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1562BE,551 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1562BE,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1562BEGA 功能描述:IC USB HOST CTRL HI-SPD 100LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話(huà) 接口:I²C，2 線(xiàn)串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤(pán)（4x4） 包裝:帶卷 (TR) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱(chēng):296-25223-2
ISP1562BEGE 功能描述:IC USB PCI HOST CTRLR 100-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話(huà) 接口:I²C，2 線(xiàn)串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤(pán)（4x4） 包裝:帶卷 (TR) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱(chēng):296-25223-2
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