![](http://datasheet.mmic.net.cn/100000/ISP1561BM-557_datasheet_3494281/ISP1561BM-557_73.png)
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
73 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
12
HCH
HC Halted: 1 = Default. This bit is logic 0 when the Run/Stop bit of
the USBCMD register is logic 1. The Host Controller sets this bit to
logic 1 after it has stopped executing because the Run/Stop bit is set
to logic 0, either by software or by the Host Controller hardware. For
example, on an internal error.
11 to 6
-
reserved
5
IAA
Interrupt on Asynchronous Advance: Default = 0. The system
software can force the Host Controller to issue an interrupt the next
time the Host Controller advances the asynchronous schedule by
writing logic 1 to the IAAD (Interrupt on Asynchronous Advance
Doorbell) bit in the USBCMD register. This status bit indicates the
assertion of that interrupt source.
4
HSE
Host System Error: The Host Controller sets this bit when a serious
error occurs during a host system access, involving the Host
Controller module. In a PCI system, conditions that set this bit
include PCI parity error, PCI master abort and PCI target abort.
When this error occurs, the Host Controller clears the RS (Run/Stop)
bit in the USBCMD register to prevent further execution of the
scheduled TDs.
3
FLR
Frame List Rollover: The Host Controller sets this bit to logic 1
when the frame list index rolls over from its maximum value to zero.
The exact value at which the rollover occurs depends on the frame
list size. For example, if the frame list size (as programmed in the
FLS (Frame List Size) eld of the USBCMD register) is 1024
elements (see
Table 111), the Frame Index register rolls over every
time bit 13 of the FRINDEX register toggles. Similarly, if the size is
512 elements, the Host Controller sets this bit to logic 1 every time
bit 12 of the FRINDEX register toggles.
2
PCD
Port Change Detect: The Host Controller sets this bit to logic 1
when any port, where the PO (Port Owner) bit is cleared, changes to
logic 1, or a Force Port Resume bit changes to logic 1 as a result of
a J-K transition detected on a suspended port. This bit is allowed to
be maintained in the auxiliary power well. Alternatively, it is also
acceptable that, on a D3-to-D0 transition of the EHCI Host Controller
device, this bit is loaded with the logical OR of all of the PORTSC
change bits, including force port resume, overcurrent change,
enable or disable change, and connect status change.
1
USBERRINT
USB Error Interrupt: The Host Controller sets this bit when an error
condition occurs because of completing a USB transaction. For
example, error counter underow. If the Transfer Descriptor (TD) on
which the error interrupt occurred also had its IOC bit set, both this
bit and USBINT bit are set.
0
USBINT
USB Interrupt: The Host Controller sets this bit on completing a
USB transaction, which results in the retirement of a TD that had its
IOC bit set. The Host Controller also sets this bit when a short
packet is detected, that is, the actual number of bytes received was
less than the expected number of bytes.
Table 106. USBSTS register: bit description …continued
Bit
Symbol
Description