參數(shù)資料
型號(hào)： ISP1561BM,557
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁(yè)數(shù)： 17/103頁(yè)
文件大小： 457K
代理商： ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
20 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
8.2.1.10
BIST register (address: 0Fh)
This register is used for control and status of Built In Self Test (BIST). Devices that do not
support BIST must always return logic 0, that is, treat it as a reserved register. A device
whose BIST is invoked must not prevent normal operation of the PCI bus. The BIST
register is not used in the ISP1561. Therefore, the logic value returned is always zero.
8.2.1.11
Base Address registers
Power-up software must build a consistent address map before booting the machine to an
operating system. This means it must determine how much memory is in the system, and
how much address space the I/O controllers in the system require. After determining this
information, power-up software can map the I/O controllers into reasonable locations and
proceed with system boot. To do this mapping in a device-independent manner, base
registers for this mapping are placed in the predened header portion of conguration
space.
Bit 0 in all Base Address registers is read-only and used to determine whether the register
maps into memory or I/O space. Base Address registers that map to memory space must
return logic 0 in bit 0. Base Address registers that map to I/O space must return logic 1 in
bit 0.
The bit description of the BAR0 register is given in Table 17.
Base Address register 0 (BAR0) — (address: 10h)
Base Address register 1, 2, 3, 4, 5 (BAR1, 2, 3, 4, 5) — (address: 14h, 18h, 1Ch, 20h
and 24h): The BAR1, 2, 3, 4, 5 register spaces are not used in the ISP1561.
8.2.1.12
CardBus CIS Pointer register (address: 28h)
This 4-byte register is used by devices that want to share silicon between CardBus and
PCI. The CardBus CIS Pointer register is used to point to the Card Information Structure
(CIS) for the CardBus card. This register is not implemented in the ISP1561.
8.2.1.13
Subsystem Vendor ID register (address: 2Ch)
The Subsystem Vendor ID register is used to uniquely identify the expansion board or
subsystem where the PCI device resides. This register allows expansion board vendors to
distinguish their boards, even though the boards may have the same vendor ID and device
ID.
Subsystem vendor IDs are assigned by PCI-SIG to maintain uniqueness. The bit
description of the Subsystem Vendor ID register is given in Table 18.
Table 17.
BAR0 register: bit description
Bit
Symbol
Access
Value
Description
31 to 0
BAR0[31:0]
R/W
0000 0000h
Base Address to Memory-Mapped Host Controller Register
Space: The memory size required by OHCI and EHCI are 4 kB and
256 bytes, respectively. Therefore, BAR0[31:12] is assigned to the two
OHCI ports, and BAR0[31:8] is assigned to the EHCI port.
Table 18.
Subsystem Vendor ID register: bit description
Bit
Symbol
Access
Value
Description
15 to 0
SVID[15:0]
R
1131h
Subsystem Vendor ID: 1131h is the subsystem vendor ID assigned to NXP
Semiconductors.
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