參數(shù)資料
型號: ISP1561BM,557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 45/103頁
文件大小: 457K
代理商: ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
46 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.1.9 HcControlHeadED register (address: content of the base address register +
20h)
The HcControlHeadED register contains the physical address of the rst ED of the control
list. The bit allocation is given in Table 59.
Bit
7
6
5
4
3
2
1
0
Symbol
PCED[3:0]
reserved
Reset
00000000
Access
RRRR
----
Table 58.
HcPeriodCurrentED register: bit description
Bit
Symbol
Description
31 to 4
PCED[27:0]
Period Current ED: This is used by the Host Controller to point to the
head of one of the periodic lists that must be processed in the current
Frame. The content of this register is updated by the Host Controller after
a periodic ED has been processed. The HCD may read the content in
determining which ED is currently being processed at the time of reading.
3 to 0
-
reserved
Table 59.
HcControlHeadED register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
CHED[27:20]
Reset
00000000
Access
RRRRRRRR
Bit
23
22
21
20
19
18
17
16
Symbol
CHED[19:12]
Reset
00000000
Access
RRRRRRRR
Bit
15
14
13
12
11
10
9
8
Symbol
CHED[11:4]
Reset
00000000
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
CHED[3:0]
reserved
Reset
00000000
Access
RRRR
----
Table 60.
HcControlHeadED register: bit description
Bit
Symbol
Description
31 to 4
CHED[27:0]
Control Head ED: The Host Controller traverses the control list,
starting with the HcControlHeadED pointer. The content is loaded
from HCCA during the initialization of the Host Controller.
3 to 0
-
reserved
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