參數(shù)資料
型號: ISP1561BM,557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 52/103頁
文件大小: 457K
代理商: ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
52 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.1.17 HcPeriodicStart register (address: content of the base address register +
40h)
The HcPeriodicStart register has a 14-bit programmable value that determines when is
the earliest time for the Host Controller to start processing the periodic list. The bit
allocation is given in Table 75.
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
--------
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
FN[13:8]
Reset
00000000
Access
-
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
FN[7:0]
Reset
00000000
Access
R/W
Table 74.
HcFmNumber register: bit description
Bit
Symbol
Description
31 to 14
-
reserved
13 to 0
FN[13:0]
Frame Number: Incremented when HcFmRemaining is re-loaded. It
must be rolled over to 0h after FFFFh. Automatically incremented when
entering the USBOPERATIONAL state. The content is written to HCCA
after the Host Controller has incremented Frame Number at each frame
boundary and sent a SOF but before the Host Controller reads the rst
ED in that frame. After writing to HCCA, the Host Controller sets the SF
(Start-of-Frame) in HcInterruptStatus.
Table 75.
HcPeriodicStart register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
--------
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
--------
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
P_S[13:8]
Reset
00000000
Access
-
R/W
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