參數(shù)資料
型號： ISP1561BM,557
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù)： 12/103頁
文件大?。?/td> 457K
代理商： ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
16 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
8.2.1.4
Status register (address: 06h)
The Status register is a 2-byte read-only register used to record status information on PCI
bus-related events (bit allocation: see Table 8).
5
VGAPS
VGA Palette Snoop: This bit controls how VGA compatible and
graphics devices handle accesses to VGA palette registers. When this
bit is logic 1, palette snooping is enabled (that is, the device does not
respond to palette register writes and snoops data). When the bit is
logic 0, the device must treat palette write accesses like all other
accesses. VGA compatible devices should implement this bit.
4
MWIE
Memory Write and Invalidate Enable: This is an enable bit for using
the Memory Write and Invalidate command. When this bit is logic 1,
masters may generate the command. When it is logic 0, Memory
Writes must be used instead. State after RST# is logic 0. This bit must
be implemented by master devices that can generate the Memory
Write and Invalidate command.
3SC
Special Cycles: Controls the action of a device on special cycle
operations. A value of logic 0 causes the device to ignore all special
cycle operations. A value of logic 1 allows the device to monitor
special cycle operations. State after RST# is logic 0.
2BM
Bus Master: Controls the ability of a device to act as a master on the
PCI bus. A value of logic 0 disables the device from generating PCI
accesses. A value of logic 1 allows the device to behave as a bus
master. State after RST# is logic 0.
1MS
Memory Space: Controls the response of a device to memory space
accesses. A value of logic 0 disables the device response. A value of
logic 1 allows the device to respond to memory space accesses. State
after RST# is logic 0.
0
IOS
IO Space: Controls the response of a device to I/O space accesses. A
value of logic 0 disables the device response. A value of logic 1 allows
the device to respond to I/O space accesses. State after RST# is
logic 0.
Table 7.
Command register: bit description …continued
Bit
Symbol
Description
Table 8.
Status register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
DPE
SSE
RMA
RTA
STA
DEVSELT[1:0]
MDPE
Reset
00000010
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
FBBC
reserved
66MC
CL
reserved
Reset
00010000
Access
R
-
R
----
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