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參數(shù)資料
| 型號： | IS80C286-20 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 38/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPU 16BIT 5V 20MHZ 68-PLCC |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 處理器類型： | 80C286 16-位 |
| 速度： | 20MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
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43
AC Test Conditions
AC Electrical Specifications VCC = +5V ±5%, TA = 0oC to +70oC (C80C286-20, -25), TA = -40oC to +85oC (l80C286-20)
AC Timings are Referenced to the 1.5V Point of the Signals as Illustrated in Data Sheet Waveforms,
Unless Otherwise Specified
SYMBOL
PARAMETER
20MHz
25MHz
UNIT
TEST CONDITION
MIN
MAX
MIN
MAX
TIMING REQUIREMENTS
1
System Clock (CLK) Period
25
-
20
-
ns
2
System Clock (CLK) LOW Time
6
-
5
-
ns
At 1.0V
3
System Clock (CLK) HIGH Time
9
-
7
-
ns
At 3.6V
17
System Clock (CLK) RISE Time
-
4
-
4
ns
1.0V to 3.6V
18
System Clock (CLK) FALL Time
-
4
-
4
ns
3.6V to 1.0V
4
Asynchronous Inputs SETUP Time
4
-
4
-
ns
(Note 37)
5
Asynchronous Inputs HOLD Time
4
-
4
-
ns
(Note 37)
6
RESET SETUP Time
10
-
10
-
ns
7
RESET HOLD Time
0
-
0
-
ns
8
Read Data SETUP Time
3
-
3
-
ns
9
Read Data HOLD Time
2
-
2
-
ns
10
READY SETUP Time
10
-
9
-
ns
11
READY HOLD Time
3-3-
ns
20
Input RISE/FALL Times
-
6
-
6
ns
0.8V to 2.0V
TIMING RESPONSES
12A
Status/PEACK Active Delay
1
15
1
12
ns
1, (Notes 39, 42)
12B
Status/PEACK Inactive Delay
1
16
1
13
ns
1, (Notes 39, 42)
13
Address Valid Delay
1
23
1
20
ns
1, (Notes 38, 39)
14
Write Data Valid Delay
0
27
0
24
ns
1, (Notes 38, 39)
15
Address/Status/Data Float Delay
0
25
0
24
ns
2, (Note 41)
16
HLDA Valid Delay
0
20
0
19
ns
1, (Notes 38, 39)
19
Address Valid to Status SETUP Time
9
-
12
-
ns
1, (Notes 39, 40)
NOTES:
37. Asynchronous inputs are INTR, NMl, HOLD, PEREQ, ERROR, and BUSY. This specification is given only for testing purposes, to assure
recognition at a specific CLK edge.
38. Delay from 1.0V on the CLK to 1.5V.
39. Output load: CL = 100pF.
40. Delay measured from address reaching 1.5V to status reaching 1.5V.
41. Delay from 1.0V on the CLK to Float (no current drive) condition.
42. Delay from 1.0V on the CLK to 1.5V.
TEST CONDITION
IL (CONSTANT CURRENT SOURCE)
CL
1
|2.0mA|
100pF
2-6mA (VOH to Float)
8mA (VOL to Float)
100pF
80C286
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