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參數(shù)資料
| 型號： | IS80C286-20 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 10/60頁 |
| 文件大小： | 0K |
| 描述： | IC CPU 16BIT 5V 20MHZ 68-PLCC |
| 標準包裝： | 18 |
| 處理器類型： | 80C286 16-位 |
| 速度： | 20MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應商設備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
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18
TABLE 10. CODE AND DATA SEGMENT DESCRIPTOR FORMATS - ACCESS RIGHTS BYTE DEFINITION
BIT
POSITION
NAME
FUNCTION
7
Present (P)
P = 1
Segment is mapped into physical memory.
P = 0
No mapping to physical memory exits, base and limit are not used.
6 - 5
Descriptor Privilege
Level (DPL)
Segment privilege attribute used in privilege tests.
4
Segment Descriptor (S) S = 1
Code or Data (includes stacks) segment descriptor
S = 0
System Segment Descriptor or Gate Descriptor
3
Executable (E)
E = 0
Data segment descriptor type is:
If Data Segment
(S = 1, E = 0)
2
Expansion Direction
(ED)
ED = 0
Expand up segment, offsets must be
≤ limit.
ED = 1
Expand down segment, offsets must be > limit.
1
Writable (W)
W = 0
Data segment may not be written into.
W = 1
Data segment may be written into.
Type
Field
Definition
3
Executable (E)
E = 1
Code Segment Descriptor type is:
If Code Segment
(S = 1, E = 1)
2
Conforming (C)
C = 1
Code segment may only be executed when CPL
≥
DPL and CPL remains unchanged.
1
Readable (R)
R = 0
Code segment may not be read.
R = 1
Code segment may be read.
0
Accessed (A)
A = 0
Segment has not been accessed.
A = 1
Segment selector has been loaded into segment register or used by selector
test instructions.
80C286
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