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參數(shù)資料
| 型號： | IS80C286-20 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 30/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPU 16BIT 5V 20MHZ 68-PLCC |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 處理器類型： | 80C286 16-位 |
| 速度： | 20MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
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36
NOTES:
11. Status lines are held at a high impedance logic one by the 80C286 during a HOLD state.
12. Address, M/IO and COD/lNTA may start floating during any TC depending on when internal 80C286 bus arbiter decides to release bus
to external HOLD. The float starts in φ2 of TC.
13. BHE and LOCK may start floating after the end of any TC depending on when internal 80C286 bus arbiter decides to release bus to
external HOLD. The float starts in φ1 of TC.
14. The minimum HOLD to HLDA time is shown. Maximum is one TH longer.
15. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown.
16. The minimum HOLD to HLDA time is shown. Maximum is a function of the instruction, type of bus cycle and other machine state (i.e.,
Interrupts, Waits, Lock, etc.).
17. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous ready state
is ignored after ready is signaled via the asynchronous input.
FIGURE 28. MULTIBUS WRITE TERMINATED BY ASYNCHRONOUS READY WITH BUS HOLD
VALID
(SEE NOTE 13)
(SEE NOTE 12)
(SEE NOTE 11)
(SEE NOTE 16)
(SEE NOTE 15)
NOT READY NOT READY
(SEE NOTE 17)
READY
(SEE NOTE 17)
DELAY ENABLE
VOH
TH
φ2
φ1
TH
φ2
φ1
TH
φ2
φ1
BUS HOLD ACKNOWLEDGE
TS
φ2
φ1
TC
φ2
φ1
TC
φ2
φ1
TC
φ2
φ1
TI
φ2
φ1
TH
φ2
φ1
BUS HOLD
ACKNOWLEDGE
WRITE CYCLE
BUS CYCLE TYPE
CLK
HOLD
(SEE NOTE 14)
HLDA
S1
S0
A23 - A0
M/IO,
D15 - D0
SRDY +
ARDY +
CMDLY
MWTC
DT/R
ALE
COD/INTA
BHE, LOCK
SRDYEN
ARDYEN
DEN
80
C
286
80C28
4
80
C288
TS - STATUS CYCLE
TC - COMMAND CYCLE
(SEE NOTE 11)
80C286
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