- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1925 > IS80C286-20 (Intersil)IC CPU 16BIT 5V 20MHZ 68-PLCC PDF資料下載
參數(shù)資料
| 型號： | IS80C286-20 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 20/60頁 |
| 文件大小： | 0K |
| 描述： | IC CPU 16BIT 5V 20MHZ 68-PLCC |
| 標準包裝： | 18 |
| 處理器類型： | 80C286 16-位 |
| 速度： | 20MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
27
synchronizes READY and RESET. The 82C288 converts
bus operation status encoded by the 80C286 into command
and bus control signals. The 82289 bus arbiter generates
Multibus bus arbitration signals. These components can
provide the critical timing required for most system bus inter-
faces including the Multibus.
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs to
CMOS devices, and to eliminate the need for pull-up/down
resistors, “bus-hold” circuitry has been used on the 80C286
pins 4-6, 36-51 and 66-68 (See Figure 19A and 19B). The
circuit shown in Figure 19A will maintain the last valid logic
state if no driving source is present (i.e. an unconnected pin
or a driving source which goes to a high impedance state).
The circuit shown in Figure 19B will maintain a high imped-
ance logic one state if no driving source is present. To over-
drive the “bus-hold” circuits, an external driver must be
capable of sinking or sourcing approximately 400 microamps
at valid input voltage levels. Since this “bus-hold” circuitry is
active and not a “resistive” type element, the associated
power supply current is negligible, and power dissipation is
significantly reduced when compared to the use of passive
pull-up resistors.
Physical Memory and I/O Interface
A maximum of 16 megabytes of physical memory can be
addressed in protected mode. One megabyte can be
addressed in real address mode. Memory is accessible as
bytes or words. Words consist of any two consecutive bytes
addressed with the least significant byte stored in the lowest
address. Byte transfers occur on either half of the 16-bit local
data bus. Even bytes are accessed over D7-0 while odd bytes
are transferred over D15-8. Even addressed words are trans-
ferred over D15-0 in one bus cycle, while odd addressed word
require two bus operations. The first transfers data on D15-8,
and the second transfers data on D7-0. Both byte data trans-
fers occur automatically, transparent to software.
Two bus signals, A0 and BHE, control transfers over the
lower and upper halves of the data bus. Even address byte
transfers are indicated by A0 LOW and BHE HIGH. Odd
address byte transfers are indicated by A0 HlGH and BHE
LOW. Both A0 and BHE are LOW for even address word
transfers.
The I/O address space contains 64K addresses in both
modes. The I/O space is accessible as either bytes or words,
as is memory. Byte wide peripheral devices may be attached
to either the upper or lower byte of the data bus. Byte-wide I/O
devices attached to the upper data byte (D15-8) are accessed
with odd I/O addresses. Devices on the lower data byte are
accessed with even I/O addresses. An interrupt controller
such as Intersil's 82C59A must be connected to the lower
data byte (D7-0) for proper return of the interrupt vector.
Bus Operation
The 80C286 uses a double frequency system clock (CLK
input) to control bus timing. All signals on the local bus are
measured relative to the system CLK input. The CPU divides
the system clock by 2 to produce the internal processor
clock, which determines bus state. Each processor clock is
composed of two system clock cycles named phase 1 and
phase 2. The 82C284 clock generator output (PCLK) identi-
fies the next phase of the processor clock. (See Figure 20.)
Six types of bus operations are supported; memory read,
memory write, I/O read, I/O write, interrupt acknowledge,
and halt/shutdown. Data can be transferred at a maximum
rate of one word per two processor clock cycles.
The 80C286 bus has three basic states: idle (TI), send sta-
tus (TS), and perform command (TC). The 80C286 CPU also
has a fourth local bus state called hold (TH). TH indicates
that the 80C286 has surrendered control of the local bus to
another bus master in response to a HOLD request.
Each bus state is one processor clock long. Figure 21 shows
the four 80C286 local bus states and allowed transitions.
EXTERNAL
PIN
OUTPUT
DRIVER
INPUT
DRIVER
INPUT
PROTECTION
CIRCUITRY
BOND
PAD
FIGURE 19A. BUS HOLD CIRCUITRY, PINS 36-51, 66, 67
EXTERNAL
PIN
OUTPUT
DRIVER
INPUT
DRIVER
INPUT
PROTECTION
CIRCUITRY
BOND
PAD
VCC
P
FIGURE 19B. BUS HOLD CIRCUITRY, PINS 4-6, 68
OF PROCESSOR
ONE PROCESSOR CLOCK CYCLE
ONE BUS T STATE
ONE SYSTEM
CLK CYCLE
PCLK
CLK
PHASE 1
CLOCK CYCLE
PHASE 2
CLOCK CYCLE
FIGURE 20. SYSTEM AND PROCESSOR CLOCK RELATION-
SHIPS
80C286
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL1532IRZ | IC LINE DRIVER DUAL 24-QFN |
| ISL1536IRZ | IC LINE DRVR DUAL ADSL2+ 16-QFN |
| ISL1539AIRZ | IC VDSL2 LINE DVR AMP 24QFN |
| ISL1539IVEZ | IC VDSL2 LINE DVR AMP 24HTTSOP |
| ISL1557AIRZ | IC LINE DRIVER DUAL 16-QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS80C31 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:CMOS SINGLE CHIP 8-BIT MICROCONTROLLER |
| IS80C31-12 | 制造商:TEMIC 功能描述:MicroController, 8-Bit, 44 Pin, Plastic, PLCC |
| IS80C31-12PL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:CMOS SINGLE CHIP 8-BIT MICROCONTROLLER |
| IS80C31-12PLI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:CMOS SINGLE CHIP 8-BIT MICROCONTROLLER |
| IS80C31-12PQ | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:CMOS SINGLE CHIP 8-BIT MICROCONTROLLER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。