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參數(shù)資料
| 型號： | IS80C286-20 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 19/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPU 16BIT 5V 20MHZ 68-PLCC |
| 標準包裝： | 18 |
| 處理器類型： | 80C286 16-位 |
| 速度： | 20MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
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26
System Interface
The 80C286 system interface appears in two forms: a local
bus and a system bus. The local bus consists of address,
data, status, and control signals at the pins of the CPU. A sys-
tem bus is any buffered version of the local bus. A system bus
may also differ from the local bus in terms of coding of status
and control lines and/or timing and loading of signals.
Bus Interface Signals and Timing
The 80C286 microsystems local bus interfaces the 80C286 to
local memory and I/O components. The interface has 24
address lines, 16 data lines, and 8 status and control signals.
The 80C286 CPU, 82C284 clock generator, 82C288 bus
controller, 82289 bus arbiter, 82C86H/87H transceivers, and
82C82/83H latches provide a buffered and decoded system
bus interface. The 82C284 generates the system clock and
LIMIT
BASE
0
15
23
0
CPU
TASK REGISTER
TYPE
DESCRIPTION
1
An available task state segment.
May be used as the destination
of a task switch operation.
3
A busy task state segment. Can-
not be used as the destination of
a task switch.
SYSTEM
SEGMENT
DESCRIPTOR
TR
RESERVED
P D
P
L
0 TYPE
BASE 15 - 0
LIMIT 15 - 0
BASE 23 - 16
TASK LDT SELECTOR
DS SELECTOR
SS SELECTOR
CS SELECTOR
ES SELECTOR
DI
SI
BP
SP
BX
DX
CX
AX
FLAG WORD
IP (ENTRY POINT)
SS FOR CPL 2
SP FOR CPL 2
SS FOR CPL 1
SP FOR CPL 1
SS FOR CPL 0
SP FOR CPL 0
BACK LINK SELECTOR TO TSS
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
CURRENT
TASK
STATE
INITIAL
STACKS
FOR CPL 0, 1, 2
BYTE
OFFSET
TASK
STATE
SEGMENT
PROGRAM INVISIBLE
15
0
15
0
P
DESCRIPTION
1
Base and Limit fields are valid.
0
Segment is not present in mem-
ory, Base and Limit are not de-
fined.
FIGURE 18. TASK STATE SEGMENT AND TSS REGISTERS
80C286
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