參數(shù)資料
型號: IS42S16800A1-7TL
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 8Meg x16 128-MBIT SYNCHRONOUS DRAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54
封裝: LEAD FREE, TSOP2-54
文件頁數(shù): 32/63頁
文件大?。?/td> 827K
代理商: IS42S16800A1-7TL
ISSI
32
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev.
00
B
0
5/01
/06
IS42S16800A1
Write
Recovering
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
X
L
L
L
L
H
H
H
X
L
L
L
L
H
H
H
X
L
L
L
L
H
H
H
X
L
L
H
H
L
L
H
X
L
L
H
H
L
L
H
X
L
L
H
H
L
L
H
X
L
L
H
H
L
L
H
X
L
H
L
H
L
H
H
X
L
H
L
H
L
H
H
X
L
H
L
H
L
H
H
X
L
H
L
H
L
H
H
X
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation; Row Active after t
DPL
No Operation; Row Active after t
DPL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Precharge after t
DPL
No Operation; Precharge after t
DPL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after t
RC
No Operation; Idle after t
RC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after two clock cycles
No Operation; Idle after two clock cycles
X
BS
BS
BS
BS
X
X
X
X
4
4
9
9
Row Address Bank Activate
Column
Column
X
X
OP Code
X
X
Row Address Bank Activate
Column
Column
X
X
OP Code
X
X
Row Address Bank Activate
Column
Column
X
X
OP Code
X
X
Row Address Bank Activate
Column
Column
X
X
Write
Read
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Write
Recovering
with
Auto Pre-
charge
X
BS
BS
BS
BS
X
X
4
4
Write
Read
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
4, 9
4, 9
Refreshing
X
BS
BS
BS
BS
X
X
Write
Read
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Mode
Register
Accessing
X
BS
BS
BS
BS
X
X
Write
Read
No Operation
Device Deselect
Current State Truth Table
(Part 3 of 3)(See note 1)
Current State
Command
Action
Notes
CS
RAS CAS
WE
BA0,BA1
A11 - A0
Description
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-
enced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (t
RAS
) must be satisfied.
7. The RAS to CAS Delay (t
RCD
) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (t
RRD
) is not satisfied.
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