參數(shù)資料
型號(hào): IS42S16800A1-7TL
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 8Meg x16 128-MBIT SYNCHRONOUS DRAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54
封裝: LEAD FREE, TSOP2-54
文件頁(yè)數(shù): 19/63頁(yè)
文件大?。?/td> 827K
代理商: IS42S16800A1-7TL
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev.
00
B
0
5/01
/06
19
ISSI
IS42S16800A1
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing auto-
precharge cannot be reactivated until t
DAL
, Data-in to Active delay, is satisfied.
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank.
It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the
write. The bank undergoing auto-precharge can not be reactivated until t
DAL
is satisfied.
Burst Write with Auto-Precharge
Burst Write with Auto-Precharge Interrupted by Write
DIN A
0
COMMAND
NOP
NOP
NOP
NOP
Auto-Precharge
DIN A
1
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
*
DIN A
0
DIN A
1
t
CK2
,
DQs
CAS latency = 2
t
CK3
,
DQs
CAS latency = 3
NOP
NOP
NOP
*
Bank can be reactivated at completion of t
DAL
.
t
DAL
is a function of clock cycle time and speed sort.
t
DAL
t
DAL
*
(Burst Length = 2, CAS Latency = 2, 3)
See the Clock Frequency and Latency table.
DIN A
0
COMMAND
NOP
NOP
NOP
*
Auto-Precharge
DIN A
1
t
DAL
CK
T0
T1
T2
T3
T4
T5
NOP
t
CK3,
DQs
CAS latency = 3
WRITE B
DIN B
0
DIN B
1
DIN B
2
DIN B
3
T6
T7
T8
NOP
NOP
NOP
*
Bank can be reactivated at completion of t
DAL
.
t
DAL
is a function of clock cycle time and speed sort.
(Burst Length = 4, CAS Latency = 3)
See the Clock Frequency and Latency table.
相關(guān)PDF資料
PDF描述
IS42S16800B-7TL 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
IS42S16800B 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
IS42S16800B-6T 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
IS42S16800B-6TL 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
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