參數(shù)資料
型號(hào): Intel386 EX
廠商: Intel Corp.
英文描述: Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器)
中文描述: 高度集成,32位,全靜態(tài)嵌入式Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器)
文件頁(yè)數(shù): 22/48頁(yè)
文件大?。?/td> 515K
代理商: INTEL386 EX
Special Environment
Intel386 EX Embedded Processor
18
PRELIMINARY
Table 10. DC Characteristics
Symbol
V
IL
V
IH
V
OL
Parameter
Min.
–0.5
0.7V
CC
Max.
0.3V
CC
V
CC
+ 0.5
Unit
V
V
Test Condition
Input Low Voltage
Input High Voltage
Output Low Voltage
All pins except Port 3
Port 3
Output High Voltage
All pins except Port 3
Port 3
Input Leakage Current
Output Leakage Current
Supply Current
0.40
0.40
V
V
V
CC
= 4.75V to 5.25V
I
OL
= 8 mA
I
OL
= 16 mA
V
CC
= 4.75V to 5.25V
I
OH
= –8 mA
I
OH
= –16 mA
0
V
IN
V
CC
0.45V
V
OUT
V
CC
25 MHz, 5.25V
Note 1
25 MHz, 5.25V
V
OH
V
CC
–0.8
V
CC
–0.8
V
V
μA
μA
mA
I
LI
I
LO
I
CC
±15
±15
250
I
IDLE
I
PD
C
S
NOTE:
1. This parameter is measured while the device is in Reset mode.
Idle Mode Current
Powerdown Current
Pin Capacitance (any pin to V
SS
)
85
100
10
mA
μA
pF
7.0
AC SPECIFICATIONS
Table 11 lists output delays, input setup require-
ments, and input hold requirements. All AC specifi-
cations are relative to the CLK2 rising edge crossing
the V
CC
/2 level.
Figure 5 shows the measurement points for AC
specifications. Inputs must be driven to the indicated
voltage levels when AC specifications are measured.
Output delays are specified with minimum and
maximum limits measured as shown. The minimum
delay times are hold times provided to external
circuitry. Input setup and hold times are specified as
minimums,
defining
the
sampling window. Within the sampling window, a
synchronous input signal must be stable for correct
operation.
smallest
acceptable
Outputs ADS#, W/R#, CS5:0#, UCS#, D/C#, M/IO#,
LOCK#, BHE#, BLE#, REFRESH#/CS6#, READY#,
LBA#, A25:1, HLDA and SMIACT# change only at
the beginning of phase one. D15:0 (write cycles) and
PWRDOWN change only at the beginning of phase
two. RD# and WR# change to their active states at
the beginning of phase two, and to their inactive
states (end of cycle) at the beginning of phase one.
The READY#, HOLD, BUSY#, ERROR#, PEREQ,
BS8#, and D15:0 (read cycles) inputs are sampled at
the beginning of phase one. The NA#, SMI#, and
NMI inputs are sampled at the beginning of phase
two.
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