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參數(shù)資料
| 型號(hào)： | Intel386 EX |
| 廠商： | Intel Corp. |
| 英文描述： | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| 中文描述： | 高度集成，32位，全靜態(tài)嵌入式Micropocessor（32位高集成完全靜態(tài)嵌入式微處理器） |
| 文件頁數(shù)： | 17/48頁 |
| 文件大?。?/td> | 515K |
| 代理商： | INTEL386 EX |
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Special Environment
Intel386 EX Embedded Processor
PRELIMINARY
13
path widths. An internal temporary register that can
disassemble or assemble data to or from either an
aligned or a nonaligned destination or source
optimizes bus bandwidth
The bus arbiter, a part of the DMA controller, works
much like the priority resolving circuitry of a DMA. It
receives service requests from the two DMA
channels, the external bus master, and the DRAM
Refresh controller. The bus arbiter requests bus
ownership from the core and resolves priority issues
among all active requests when bus mastership is
granted.
Each DMA channel consists of three major compo-
nents: the Requestor, the Target, and the Byte
Count. These components are identified by the
contents of programmable registers that define the
memory or I/O device being serviced by the DMA.
The Requestor is the device that requires and
requests service from the DMA controller. Only the
Requestor is considered capable of initializing or
terminating a DMA process. The Target is the device
with which the Requestor wishes to communicate.
The DMA process considers the Target a slave that
is incapable of controlling the process. The Byte
Count dictates the amount of data that must be
transferred.
4.10
Refresh Control Unit
The Refresh Control Unit (RCU) simplifies dynamic
memory controller design with its integrated address
and clock counters. Integrating the RCU into the
processor allows an external DRAM controller to use
chip-selects, wait state logic, and status lines. The
RCU consists of:
a programmable-interval timer that keeps track of
time
bus arbitration logic to gain control of the bus to
run refresh cycles
row address generation logic to individually refresh
DRAM rows
refresh cycle-start logic
The 13-bit address counter that forms the refresh
address supports DRAM with up to 13 rows of
memory cells (13 refresh address bits). This includes
all practical DRAM sizes for the 64 Mbyte address
space.
4.11
JTAG Test-logic Unit
The JTAG Test-Logic Unit (TLU) provides access to
the device pins and to a number of other testable
areas on the device. It is fully compliant with the
IEEE 1149.1 standard and thus interfaces with five
dedicated pins: TRST#, TCK, TMS, TDI, and TDO. It
contains the Test Access Port (TAP) finite-state
machine, a 4-bit instruction register, a 32-bit identifi-
cation register, and a single-bit bypass register. The
TLU also contains the necessary logic to generate
clock and control signals for the Boundary Scan
chain.
Since the TLU has its own clock and reset signals, it
can operate autonomously. Thus, while the rest of
the processor is in Reset or Powerdown, the JTAG
unit can read or write various register chains.
5.0
DESIGN CONSIDERATIONS
This section describes the instruction set and
component and revision identifiers.
5.1
Instruction Set
The Special Environment Intel386 EX embedded
processor uses the same instruction set as the
Intel386 SX microprocessor with the following
exceptions:
The Special Environment Intel386 EX
embedded processor has one new instruction: the
Resume instruction (RSM). It causes the
processor to exit System Management Mode
(SMM).
The Special Environment Intel386 EX
embedded processor requires more clock cycles
than the Intel386 SX microprocessor to execute
some instructions.
Table 7 lists these instructions and the Intel386 EX
microprocessor Clocks Per Instructions (CPI). For
the equivalent Intel386 SX microprocessor CPI, refer
to the “Instruction Set Clock Count Summary” table
in the Intel386 SX Microprocessor
data sheet
(order number 240187).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| Intel387 sx | SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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