參數(shù)資料
型號(hào)： Intel386 EX
廠商： Intel Corp.
英文描述： Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器)
中文描述： 高度集成，32位，全靜態(tài)嵌入式Micropocessor（32位高集成完全靜態(tài)嵌入式微處理器）
文件頁(yè)數(shù)： 16/48頁(yè)
文件大?。?/td> 515K
代理商： INTEL386 EX
Special Environment
Intel386 EX Embedded Processor
12
PRELIMINARY
4.4
Timer Control Unit
The Timer Control Unit (TCU) has the same basic
functionality
as
the
industry-standard
counter/timer. The TCU provides three independent
16-bit counters, each capable of handling clock
inputs up to 8 MHz. This maximum frequency must
be considered when programming the input clocks
for the counters. Six programmable timer modes
allow the counters to be used as event counters,
elapsed-time indicators, programmable one-shots,
and in many other applications. All modes are
software programmable.
82C54
4.5
Watchdog Timer Unit
The Watchdog Timer (WDT) unit consists of a 32-bit
down-counter that decrements every PH1P cycle,
allowing up to 4.3 billion count intervals. The
WDTOUT pin is driven high for sixteen CLK2 cycles
when the down-counter reaches zero (the WDT
times out). The WDTOUT signal can be used to
reset the chip, to request an interrupt, or to indicate
to the user that a ready-hang situation has occurred.
The down-counter can also be updated with a user-
defined 32-bit reload value under certain conditions.
Alternatively, the WDT unit can be used as a bus
monitor or as a general-purpose timer.
4.6
Asynchronous Serial I/O Unit
The asynchronous Serial I/O (SIO) unit is a
Universal
Asynchronous
(UART). Functionally, it is equivalent to the National
Semiconductor* NS16450 and INS8250. The
Special Environment Intel386 EX embedded
processor contains two full-duplex, asynchronous
serial channels.
Receiver/Transmitter
The SIO unit converts serial data characters
received from a peripheral device or modem to
parallel data and converts parallel data characters
received from the CPU to serial data. The CPU can
read the status of the serial port at any time during
its operation. The status information includes the
type and condition of the transfer operations being
performed and any errors (parity, framing, overrun,
or break interrupt).
Each asynchronous serial channel includes full
modem control support (CTS#, RTS#, DSR#, DTR#,
RI#, and DCD#) and is completely programmable.
The programmable options include character length
(5, 6, 7, or 8 bits), stop bits (1, 1.5, or 2), and parity
(even, odd, forced, or none). In addition, it contains a
programmable baud-rate generator capable of clock
rates from 0 to 512 Kbaud.
4.7
Synchronous Serial I/O Unit
The Synchronous Serial I/O (SSIO) unit provides for
simultaneous,
bidirectional
consists of a transmit channel, a receive channel,
and a dedicated baud-rate generator. The transmit
and receive channels can be operated indepen-
dently (with different clocks) to provide non-lockstep,
full-duplex communications; either channel can
originate the clocking signal (Master Mode) or
receive an externally generated clocking signal
(Slave Mode).
communications.
It
The SSIO provides numerous features for ease and
flexibility of operation. With a maximum clock input of
12.5 MHz to the baud-rate generator, the SSIO can
deliver a baud rate of 5 Mbits per second. Each
channel is double buffered. The two channels share
the baud-rate generator and a multiply-by-two
transmit and receive clock. The SSIO supports 16-bit
serial communications with independently enabled
transmit and receive functions and gated interrupt
outputs to the interrupt controller.
4.8
Parallel I/O Unit
The Special Environment Intel386 EX embedded
processor has three 8-bit, general-purpose I/O ports.
All port pins are bidirectional, with CMOS-level input
and outputs. All pins have both a standard operating
mode and a peripheral mode (a multiplexed
function), and all have similar sets of control
registers located in I/O address space. Ports 1 and 2
provide 8 mA of drive capability, while port 3
provides 16 mA.
4.9
DMA and Bus Arbiter Unit
The DMA controller is a two-channel DMA; each
channel operates independently of the other. Within
the operation of the individual channels, several
different data transfer modes are available. These
modes can be combined in various configurations to
provide a very versatile DMA controller. Its feature
set has enhancements beyond the 8237 DMA
family; however, it can be configured such that it can
be used in an 8237-like mode. Each channel can
transfer data between any combination of memory
and I/O with any combination (8 or 16 bits) of data
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