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參數(shù)資料
| 型號： | Intel386 EX |
| 廠商： | Intel Corp. |
| 英文描述： | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| 中文描述： | 高度集成，32位，全靜態(tài)嵌入式Micropocessor（32位高集成完全靜態(tài)嵌入式微處理器） |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 515K |
| 代理商： | INTEL386 EX |
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Special Environment
Intel386 EX Embedded Processor
10
PRELIMINARY
STXCLK
I/O
SSIO Transmit Clock
synchronizes data being sent by the synchronous serial
port. STXCLK is multiplexed with DSR1.
TAP (Test Access Port) Controller Clock
provides the clock input for the JTAG
logic.
TAP (Test Access Port) Controller Data Input
is the serial input for test instruc-
tions and data.
TAP (Test Access Port) Controller Data Output
is the serial output for test
instructions and data.
Timer/Counter Clock Inputs
can
serve as external clock inputs for the corre-
sponding timer/counters. (The timer/counters can also be clocked internally.)
They are multiplexed as follows: TMRCLK2 with PEREQ, TMRCLK1 with INT6,
and TMRCLK0 with INT4.
Timer/Counter Gate Inputs
can control the corresponding timer/counter’s
counting (enable, disable, or trigger, depending on the programmed mode). They
are multiplexed as follows: TMRGATE2 with BUSY#, TMRGATE1 with INT7, and
TMRGATE0 with INT5.
Timer/Counter Outputs
provide the output of the corresponding timer/counter.
The form of the output depends on the programmed mode. They are multiplexed
as follows: TMROUT2 with ERROR#, TMROUT1 with P3.1, and TMROUT0 with
P3.0.
TAP (Test Access Port) Controller Mode Select
controls the sequence of the
TAP controller’s states.
TAP (Test Access Port) Controller Reset
resets the TAP controller at power-up
and each time it is activated.
Transmit Data SIO1 and SIO0
transmit serial data from the individual serial
channels. TXD1 is multiplexed with DACK1#, and TXD0 is multiplexed with P2.6.
Upper Chip-select
is activated when the address of a memory or I/O bus cycle is
within the address region programmed by the user.
System Power
provides the nominal DC supply input. Connected externally to a
V
CC
board plane.
System Ground
provides the 0V connection from which all inputs and outputs
are measured. Connected externally to a ground board plane.
Watchdog Timer Output
indicates that the watchdog timer has expired.
Write/Read
indicates whether the current bus cycle is a write cycle or a read
cycle. When W/R# is high, the bus cycle is a write cycle; when W/R# is low, the
bus cycle is a read cycle.
Write Enable
indicates that the current bus cycle is a write cycle.
TCK
I
TDI
I
TDO
O
TMRCLK2:0
I
TMRGATE2:0
I
TMROUT2:0
O
TMS
I
TRST#
ST
TXD1:0
O
UCS#
O
V
CC
P
V
SS
G
WDTOUT
W/R#
O
O
WR#
O
Table 3. Pin Descriptions
(Sheet 4 of 4)
Symbol
Type
Name and Function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| Intel387 sx | SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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