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參數(shù)資料
| 型號： | Intel386 EX |
| 廠商： | Intel Corp. |
| 英文描述： | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| 中文描述： | 高度集成，32位，全靜態(tài)嵌入式Micropocessor（32位高集成完全靜態(tài)嵌入式微處理器） |
| 文件頁數(shù)： | 13/48頁 |
| 文件大?。?/td> | 515K |
| 代理商： | INTEL386 EX |
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Special Environment
Intel386 EX Embedded Processor
PRELIMINARY
9
PEREQ
I
Processor Extension Request
indicates that the math coprocessor has data to
transfer to the processor. PEREQ is multiplexed with TMRCLK2.
Port 1, Pins 7:0
are multipurpose bidirectional port pins. They are multiplexed as
follows: P1.7 with HLDA, P1.6 with HOLD, P1.5 with LOCK#, P1.4 with RI0#,
P1.3 with DSR0#, P1.2 with DTR0#, P1.1 with RTS0#, and P1.0 with DCD0#.
Port 2, Pins 7:0
are multipurpose bidirectional port pins. They are multiplexed as
follows: P2.7 with CTS0#, P2.6 with TXD0, P2.5 with RXD0, and P2.4:0 with
CS4:0#.
Port 3, Pins 7:0
are multipurpose bidirectional port pins. They are multiplexed as
follows: P3.7 with COMCLK, P3.6 with PWRDOWN, P3.5:2 with INT3:0, and
P3.1:0 with TMROUT1:0.
Powerdown
indicates that the processor is in powerdown mode. PWRDOWN is
multiplexed with P3.6.
Read
Enable
indicates that the current bus cycle is a read cycle.
Ready
indicates that the current bus transaction has completed. An external
device or an internal signal can drive READY#. Internally, the chip-select wait-
state logic can generate the ready signal and drive the READY# pin active.
Reset
suspends any operation in progress and places the processor into a known
reset state.
Refresh
indicates that the current bus cycle is a refresh cycle. REFRESH# is
multiplexed with CS6#.
Ring Indicator SIO1 and SIO0
indicate that the modem or data set has received
a telephone ringing signal. RI1# is multiplexed with SSIORX, and RI0# is
multiplexed with P1.4.
Request-to-send SIO1 and SIO0
indicate that corresponding asynchronous
serial channel is ready to exchange data with the modem or data set. RTS1# is
multiplexed with SSIOTX, and RTS0# is multiplexed with P1.1.
Receive Data SIO1 and SIO0
accept serial data from the modem or data set to
the corresponding asynchronous serial channel. RXD1 is multiplexed with DRQ1,
and RXD0 is multiplexed with P2.5.
System Management Interrupt
invokes System Management Mode (SMM).
SMI# is the highest priority external interrupt. It is latched on its falling edge and it
forces the CPU into SMM upon completion of the current instruction. SMI# is
recognized on an instruction boundary and at each iteration for repeat string
instructions. SMI# cannot interrupt LOCKed bus cycles or a currently executing
SMM. If the processor receives a second SMI# while it is in SMM, it will latch the
second SMI# on the SMI# falling edge. However, the processor must exit SMM by
executing a resume instruction (RSM) before it can service the second SMI#.
System Management Interrupt Active
indicates that the processor is operating
in System Management Mode (SMM). It is asserted when the processor initiates
an SMM sequence and remains asserted (low) until the processor executes the
resume instruction (RSM).
SSIO Receive Clock
synchronizes data being accepted by the synchronous
serial port. SRXCLK is multiplexed with DTR1#.
SSIO Receive Serial Data
accepts serial data (most-significant bit first) being
sent to the synchronous serial port. SSIORX is multiplexed with RI1#.
SSIO Transmit Serial Data
sends serial data (most-significant bit first) from the
synchronous serial port. SSIOTX is multiplexed with RTS1#.
P1.7:0
I/O
P2.7:0
I/O
P3.7:0
I/O
PWRDOWN
O
RD#
READY#
O
I/O
RESET
ST
REFRESH#
O
RI1:0#
I
RTS1:0#
O
RXD1:0
I
SMI#
ST
SMIACT#
O
SRXCLK
I/O
SSIORX
I
SSIOTX
O
Table 3. Pin Descriptions
(Sheet 3 of 4)
Symbol
Type
Name and Function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| Intel387 sx | SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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