參數(shù)資料
型號(hào)： IDTSSTE32882KA1AKG
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 42/75頁(yè)
文件大?。?/td> 0K
描述： IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝： 170
類(lèi)型： 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器
PLL： 是
主要目的： 存儲(chǔ)器，DDR3，RDIMM
輸入： CMOS
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 5:60
差分 - 輸入:輸出： 是/是
頻率 - 最大： 810MHz
電源電壓： 1.282 V ~ 1.575 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 176-TFBGA
供應(yīng)商設(shè)備封裝： 176-CABGA（13.5x8）
包裝： 托盤(pán)
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
47
SSTE32882KA1
7314/8
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
CLOCK STOPPED POWER DOWN MODE
To support S3 Power Management mode or any other operation that allows Yn clocks to float, the SSTE32882KA1 supports a
Clock Stopped power down mode. When both inputs CK and CK are being held LOW, (VIL(static)) or float (will eventually
settle at LOW because of the (10K-100K Ohm) pulldown resistor in the CK/CK input buffer, the device stops operation and
enters low-power static and standby operation. The corresponding timing are shown in “Clock Stopped Power Down Entry and
Exit with IBT On” and “Clock Stopped Power Down Entry and Exit with IBT Off“. The register device will stop its PLL and
floats all outputs except QACKE0, QACKE1, QBCKE0 and QBCKE1, which must be kept driven LOW.
The Clock Stopped power down mode can only be utilized once the DRAM received a self refresh command. In this state, the
DRAM ignores all inputs except CKE. Hence, all register outputs besides QxCKE0 and QxCKE1 can be disabled.
Clock Stopped Power Down Mode Entry
To enter Clock Stopped Power Down mode, the register will first enter CKE power down mode. Once in CKE power down
mode, the host will deasserts DCKEn for a minimum of one tCKoff before pulling CK and CK LOW. After holding CK and
CK LOW (VIL(static)) for at least one tCKEV, both CK and CK can be floated (because of the (10K-100K Ohm) pulldown
resistor in the CK/CK input buffer, CK/CK will stay at LOW even though they are not being driven).The register is now in
Clock Stopped Power Down mode.
After CK and CK are pulled LOW, the host has to keep DCKEn stable for at least one tCKEV before it can float DCKEn. At this
point, all input receivers and input termination of the SSTE32882KA1 are disabled. The only active input circuits are CK and
CK, which are required to detect the wake up request from the host.
Clock Stopped Power Down Mode Exit
To wake up the register after Clock Stopped power down, the host must drive the register inputs DCS[n:0] must be driven to
HIGH (to prevent accidental access to the control registers), and DCKEn to LOW. After that, the host can apply a frequency
and phase accurate input clock signal. Within tACT after CK and CK resumed normal operation, the SSTE32882KA1 outputs
start becoming a function of their corresponding inputs. The state of the DCS[n:0] inputs must not be changed before the end
of tSTAB. The input clock CK and CK must be stable for a time equal or greater than tSTAB before any access to the
SSTE32882KA1 can takes place.
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參數(shù)描述
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