參數(shù)資料
型號(hào): IDTSSTE32882KA1AKG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 3/75頁(yè)
文件大?。?/td> 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝: 170
類型: 時(shí)鐘緩沖器/驅(qū)動(dòng)器,多路復(fù)用器
PLL:
主要目的: 存儲(chǔ)器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應(yīng)商設(shè)備封裝: 176-CABGA(13.5x8)
包裝: 托盤(pán)
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
11
SSTE32882KA1
7314/8
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Function Table (Each Flip Flop) with QuadCS Mode Disabled
Power
Vrefca1
Reference Voltage
Input reference voltage for the differential data inputs, VDD/2
(0.75V) nominal.
Vdd
Register Power
Power supply voltage (Register)
Vss
Register Ground
Ground (Register)
AVdd
Analog Power
Analog supply voltage (PLL)
AVss
Analog Ground
Analog ground (PLL)
PVdd
PLL Power
Clock logic and clock output driver power supply (PLL)
PVss
PLL Ground
Clock logic and clock output driver ground (PLL)
RSVD
I/O
Reserved pins, must be left floating (PLL)
1
1.25V/1.35V/1.5V CMOS inputs use VREFCA as the switching point reference for these receivers.
2
These outputs are optimized for memory applications to drive DRAM inputs to 1.25V/1.35V/1.5V signaling levels.
3
Voltage levels according standard JESD8-11A, wide range, non terminated logic.
Inputs
Outputs1
1
Q0 means the output does not change state.
RESET
DCS0
DCS1
CK2
2
It is illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels (LOW and HIGH) when
RESET is driven HIGH.
ADDR3
3
ADDR = DA[15:0], DBA[2:0]
CMD4
4
CMD = DRAS, DCAS, DWE.
CTRL5
5
CTRL = DODTn, DCKEn.
Qn6
6
Qn = QxAn, QxRAS, QxCAS, QxWE, and QxBAn.
QxCS0
QxCS1
QxODTn
QxCKEn
HL
L
↑↓
Control
Word
Control
Word
Control
Word
Q0
HH
Q0
H
X
L or H H or L
X
Q0
HL
H
↑↓
XX
X
Follows
Input
LH
Follows
Input
Follows
Input
H
X
L
X
float
L
HH
L
↑↓
XX
X
Follows
Input
HL
Follows
Input
Follows
Input
HH
H
↑↓
X or
float
X or float
X
Q0 or
float7
7
Depending on Control Word RC0 Bit DA4. If RC0 DA4 is cleared, previous state (Q0) is maintained. Address floating is
disabled independent of control word RC0 once 3T timing is activated.
HH
Follows
Input
Follows
Input
L
X or
float
X or
float
X or
float
X or
float
X or
float
X or float
X or
float
L
Signal Group
Signal Name
Type
Description
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