參數(shù)資料
型號： IDT82V3255TFG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 91/132頁
文件大小： 0K
描述： IC PLL WAN SMC STRATUM 3 64-TQFP
標準包裝： 1,250
類型： 時鐘/頻率發(fā)生器，多路復用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 3:3
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應商設備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
其它名稱： 82V3255TFG8
IDT82V3255
WAN PLL
Programming Information
61
December 3, 2008
INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2
INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3
Address: 11H
Type: Read / Write
Default Value:00XXXXX0
Bit
Name
Description
7
T0_OPERATING_MODE
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 DPLL operating mode
switches, i.e., when the T0_OPERATING_MODE bit (b7, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
6
T0_MAIN_REF_FAILED
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 selected input clock
has failed; i.e., when the T0_MAIN_REF_FAILED bit (b6, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
5 - 1
-
Reserved.
0IN3_CMOS
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity
changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding IN3_CMOS bit (b0, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
Address: 12H
Type: Read / Write
Default Value: 00X0XXXX
Bit
Name
Description
7
EX_SYNC_ALARM
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when an external sync alarm has
occurred, i.e., when the EX_SYNC_ALARM bit (b7, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
6T4_STS
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T4 DPLL locking status
changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’), i.e., when the T4_STS bit (b6, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
5-
Reserved.
4
INPUT_TO_T4
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when all the input clocks for T4 path
change to be unqualified, i.e., when the INPUT_TO_T4 bit (b4, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
3 - 0
-
Reserved.
7
6
54321
0
T0_OPERATING
_MODE
T0_MAIN_REF_F
AILED
-
----
IN3_CMOS
7
6543210
EX_SYNC_ALARM
T4_STS
-
INPUT_TO_T4
-
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相關代理商/技術參數(shù)
參數(shù)描述
IDT82V3255TFGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3280 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
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IDT82V3280APFG 功能描述:IC PLL WAN SE STRATUM 2 100TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3280APFG8 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 2 100TQFP
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