IDT82V3255
WAN PLL
Electrical Specifications
118
December 3, 2008
Table 46: Output Clock Phase Noise
Output Clock 1
@100Hz Offset
Typ
@1kHz Offset
Typ
@10kHz Offset
Typ
@100kHz Offset
Typ
@1MHz Offset
Typ
@5MHz Offset
Typ
Unit
622.08 MHz (T0 DPLL + T0/T4 APLL)
-70
-86
-95
-100
-107
-128
dBC/Hz
155.52 MHz (T0 DPLL + T0/T4 APLL)
-82
-98
-107
-112
-119
-140
dBC/Hz
38.88 MHz (T0 DPLL + T0/T4 APLL)
-94
-110
-118
-124
-131
-143
dBC/Hz
16E1 (T0/T4 APLL)
-94
-110
-118
-125
-131
-142
dBC/Hz
16T1 (T0/T4 APLL)
-95
-112
-120
-127
-132
-143
dBC/Hz
E3 (T0/T4 APLL)
-93
-109
-116
-124
-131
-138
dBC/Hz
T3 (T0/T4 APLL)
-92
-108
-116
-122
-126
-141
dBC/Hz
Note:
1. CMAC E2747 TCXO is used.
Table 47: Input Jitter Tolerance (155.52 MHz)
Jitter Frequency
Jitter Tolerance Amplitude (UI p-p)
12
Hz
> 2800
178
Hz
> 2800
1.6 mHz
> 311
15.6 mHz
> 311
0.125 Hz
> 39
19.3 Hz
> 39
500 Hz
> 1.5
6.5 kHz
> 1.5
65 kHz
> 0.15
1.3 MHz
> 0.15
Table 48: Input Jitter Tolerance (1.544 MHz)
Jitter Frequency
Jitter Tolerance Amplitude (UI p-p)
1 Hz
150
5 Hz
140
20 Hz
130
300 Hz
38
400 Hz
25
700 Hz
15
2400 Hz
5
10 kHz
1.2
40 kHz
0.5
Table 49: Input Jitter Tolerance (2.048 MHz)
Jitter Frequency
Jitter Tolerance Amplitude (UI p-p)
1 Hz
150
5 Hz
140
20 Hz
130
300 Hz
40
400 Hz
33
700 Hz
18
2400 Hz
5.5
10 kHz
1.3
50 kHz
0.4
100 kHz
0.4
Table 50: Input Jitter Tolerance (8 kHz)
Jitter Frequency
Jitter Tolerance Amplitude (UI p-p)
1 Hz
0.8
5 Hz
0.7
20 Hz
0.6
300 Hz
0.16
400 Hz
0.14
700 Hz
0.07
2400 Hz
0.02
3600 Hz
0.01