參數(shù)資料
型號: IDT82V3255TFG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 117/132頁
文件大小: 0K
描述: IC PLL WAN SMC STRATUM 3 64-TQFP
標準包裝: 1,250
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 3:3
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 82V3255TFG8
IDT82V3255
WAN PLL
Programming Information
85
December 3, 2008
PRIORITY_TABLE1_STS - Priority Status 1 *
Address: 4EH
Type: Read
Default Value: 00000000
Bit
Name
Description
7 - 4
HIGHEST_PRIORITY_VALIDATED[3:0]
These bits indicate a qualified input clock with the highest priority.
0000: No input clock is qualified. (default)
0001, 0010: Reserved.
0011: IN1_CMOS.
0100: IN2_CMOS.
0101: IN1_DIFF.
0110: IN2_DIFF.
0111, 1000: Reserved.
1001: IN3_CMOS.
1010 ~ 1111: Reserved.
3 - 0
CURRENTLY_SELECTED_INPUT[3:0]
These bits indicate the T0/T4 selected input clock.
0000: No input clock is selected; or the T4 selected input clock is the T0 DPLL output. (default)
0001, 0010: Reserved.
0011: IN1_CMOS is selected.
0100: IN2_CMOS is selected.
0101: IN1_DIFF is selected.
0110: IN2_DIFF is selected.
0111, 1000: Reserved.
1001: IN3_CMOS is selected.
1010 ~ 1111: Reserved.
7
6543
210
HIGHEST_PRI
ORITY_VALIDA
TED3
HIGHEST_PRI
ORITY_VALIDA
TED2
HIGHEST_PRI
ORITY_VALIDA
TED1
HIGHEST_PRI
ORITY_VALIDA
TED0
CURRENTLY_S
ELECTED_INP
UT3
CURRENTLY_S
ELECTED_INP
UT2
CURRENTLY_S
ELECTED_INP
UT1
CURRENTLY_S
ELECTED_INP
UT0
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