參數(shù)資料
型號： IDT82V3255TFG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 83/132頁
文件大小： 0K
描述： IC PLL WAN SMC STRATUM 3 64-TQFP
標(biāo)準(zhǔn)包裝： 1,250
類型： 時鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 3:3
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
其它名稱： 82V3255TFG8
IDT82V3255
WAN PLL
Programming Information
54
December 3, 2008
INPUT_MODE_CNFG - Input Mode Configuration
Address: 09H
Type: Read / Write
Default Value: 10100X10
Bit
Name
Description
7
AUTO_EXT_SYNC_EN
This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is ‘0’.
Refer to the description of the EXT_SYNC_EN bit (b6, 09H).
6
EXT_SYNC_EN
This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is ‘0’.
This bit, together with the AUTO_EXT_SYNC_EN bit (b7, 09H), determines whether the selected frame sync input signal is
enabled to synchronize the frame sync output signals.
5
PH_ALARM_TIMEOUT
This bit determines how to clear the phase lock alarm.
0: The phase lock alarm will be cleared when a ‘1’ is written to the corresponding INn_CMOS_PH_LOCK_ALARM (n = 1, 2
or 3) / INn_DIFF_PH_LOCK_ALARM (n = 1 or 2) bit (b4/0, 44H/45H/47H).
1: The phase lock alarm will be cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0]
(b7~6, 08H) in second) which starts from when the alarm is raised. (default)
4 - 3
SYNC_FREQ[1:0]
These bits set the frequency of the frame sync signals input on the EX_SYNC1 ~ EX_SYNC3 pins.
00: 8 kHz (default)
01: 8 kHz.
10: 4 kHz.
11: 2 kHz.
2
IN_SONET_SDH
This bit selects the SDH or SONET network type.
0: SDH. The DPLL required clock is 2.048 MHz when the IN_FREQ[3:0] bits (b3~0, 16H, 17H, 19H, 1AH & 1DH) are ‘0001’
and the T0/T4 DPLL output from the 16E1/16T1 path is 16E1.
1: SONET. The DPLL required clock is 1.544 MHz when the IN_FREQ[3:0] bits (b3~0, 16H, 17H, 19H, 1AH & 1DH) are
‘0001’ and the T0/T4 DPLL output from the 16E1/16T1 path is 16T1.
The default value of this bit is determined by the SONET/SDH pin during reset.
1-
Reserved.
0
REVERTIVE_MODE
This bit selects Revertive or Non-Revertive switch for T0 path.
0: Non-Revertive switch. (default)
1: Revertive switch.
76543210
AUTO_EXT_SY
NC_EN
EXT_SYNC_EN
PH_ALARM_TI
MEOUT
SYNC_FREQ1
SYNC_FREQ0
IN_SONET_SD
H
-
REVERTIVE_M
ODE
AUTO_EXT_SYNC_EN EXT_SYNC_EN
Synchronization
don’t-care
0
Disabled (default)
01
Enabled
11
Disabled
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