參數(shù)資料
型號(hào): IDT82P2816BBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 62/146頁
文件大小: 0K
描述: IC LINE INTERFACE UNIT 416-PBGA
標(biāo)準(zhǔn)包裝: 5
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 1
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 416-BGA
供應(yīng)商設(shè)備封裝: 416-PBGA(27x27)
包裝: 托盤
包括: 缺陷和警報(bào)檢測,驅(qū)動(dòng)器過流檢測和保護(hù),LLOS 檢測,PRBSARB / IB 檢測和生成
產(chǎn)品目錄頁面: 1259 (CN2011-ZH PDF)
其它名稱: 800-1702
82P2816BBG
IDT82P2816
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Pin Description
22
February 6, 2009
SDO / ACK / RDY
Output
AE17
SDO: Serial Data Output
In Serial microprocessor interface, this multiplex pin is used as SDO.
Data on this pin is serially clocked out of the device on the falling edge of SCLK.
ACK: Acknowledge Output (Active Low)
In Parallel Motorola microprocessor interface, this multiplex pin is used as ACK.
A low level on ACK indicates that valid information on the data bus is ready for a read opera-
tion or acknowledges the acceptance of the written data during a write operation.
RDY: Ready Output
In Parallel Intel microprocessor interface, this multiplex pin is used as RDY.
A high level on RDY reports to the microprocessor that a read/write cycle can be completed. A
low level on RDY reports that wait states must be inserted.
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
Output / Input
AF13
AC12
AD12
AE12
AF12
AD11
AE11
AF11
D[7:0]: Bi-directional Data Bus
In Parallel Motorola /Intel Non-Multiplexed microprocessor interface, these pins are the bi-
directional data bus of the microprocessor interface.
In Parallel Motorola /Intel Multiplexed microprocessor interface, these pins are the multiplexed
bi-directional address /data bus.
In Serial microprocessor interface, these pins should be connected to GNDD.
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
Input
AE16
AF16
AD15
AE15
AF15
AC14
AD14
AE14
AF14
AD13
AE13
A[10:0]: Address Bus
In Parallel Motorola /Intel Non-Multiplexed microprocessor interface, these pins are the
address bus of the microprocessor interface.
In Parallel Motorola /Intel Multiplexed microprocessor interface, A[10:8], together with D[7:0],
are the address bus; while A[7:0] should be connected to GNDD.
In Serial microprocessor interface, these pins should be connected to GNDD.
JTAG (per IEEE 1149.1)
TRST
Input
Pull-Down
AE7
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port. To ensure deterministic operation of the test
logic, TMS should be held high when the signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-down resistor.
TMS
Input
Pull-up
AD7
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK. To ensure deterministic operation of the test logic, TMS should be held high when the
signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-up resistor.
TCK
Input
AE8
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
When TCK is idle at low state, all stored-state devices contained in the test logic shall retain
their state indefinitely.
This pin should be connected to GNDD when JTAG is not used.
Name
I / O
Pin No.
Description
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