參數(shù)資料
型號: IDT82P2816BBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 122/146頁
文件大?。?/td> 0K
描述: IC LINE INTERFACE UNIT 416-PBGA
標(biāo)準包裝: 5
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 1
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 416-BGA
供應(yīng)商設(shè)備封裝: 416-PBGA(27x27)
包裝: 托盤
包括: 缺陷和警報檢測,驅(qū)動器過流檢測和保護,LLOS 檢測,PRBSARB / IB 檢測和生成
產(chǎn)品目錄頁面: 1259 (CN2011-ZH PDF)
其它名稱: 800-1702
82P2816BBG
IDT82P2816
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Programming Information
77
February 6, 2009
CLKG - CLKT1 & CLKE1 Generation Control Register
REFCF - REFA/B Output Configuration Register
Address: 1C0H
Type: Read / Write
Default Value: 0FH
Bit
Name
Description
7 - 4
-
Reserved.
3
CLKE1_EN
This bit controls whether the output on the CLKE1 pin is enabled.
0: The output is disabled. CLKE1 is in High-Z state.
1: The output is enabled. The frequency of CLKE1 is determined by the CLKE1 bit (b2, CLKG). (default)
2
CLKE1
This bit is valid only when the CLKE1_EN bit (b3, CLKG) is ‘1’. This bit selects the clock frequency output on the CLKE1 pin.
0: 8 KHz.
1: 2.048 MHz. (default)
1
CLKT1_EN
This bit controls whether the output on the CLKT1 pin is enabled.
0: The output is disabled. CLKT1 is in High-Z state.
1: The output is enabled. The frequency of CLKT1 is determined by the CLKT1 bit (b0, CLKG). (default)
0
CLKT1
This bit is valid only when the CLKT1_EN bit (b1, CLKG) is ‘1’. This bit selects the clock frequency output on the CLKT1 pin.
0: 8 KHz.
1: 1.544 MHz. (default)
Address: 200H
Type: Read / Write
Default Value: 30H
Bit
Name
Description
7-
Reserved.
6
JA_BYPAS
This bit is valid only when the clock source for REFA or REFB is the recovered clock of one of the 17 channels in the correspond-
ing receiver. This bit determines whether the selected recovered clock passes through the RJA.
0: The selected recovered clock is derived from the output of RJA. (default)
1: The selected recovered clock does not pass through the RJA and is derived from the output of Rx Clock & Data Recovery.
5
REFH
This bit is valid only when the selected clock source is lost. This bit controls the output on REFA/REFB.
For REFA, this bit, together with the FS_BYPAS bit (b4, REFCF) and the FREE bit (b3, REFCF), controls the output on REFA
when the selected clock source is the recovered clock of one of the 17 channels; this bit is ignored when the selected clock
source is CLKA. Refer to the related table in the description of the FREE bit (b3, REFCF).
For REFB:
0: Output free running clock. The frequency is 1.544 MHz if the selected clock source was T1 clock or 2.048 MHz if the selected
clock source was E1 clock.
1: Output high level. (default)
4
FS_BYPAS
This bit determines whether the selected clock source for REFA passes through an internal Frequency Synthesizer.
0: The internal Frequency Synthesizer is enabled.
1: The internal Frequency Synthesizer is bypassed. (default)
7
654
321
0
-
CLKE1_EN
CLKE1
CLKT1_EN
CLKT1
7654321
0
-
JA_BYPAS
REFH
FS_BYPAS
FREE
FREQ2
FREQ1
FREQ0
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