參數(shù)資料
型號(hào)： IDT82P2816BBG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 137/146頁
文件大?。?/td> 0K
描述： IC LINE INTERFACE UNIT 416-PBGA
標(biāo)準(zhǔn)包裝： 5
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 1
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 416-BGA
供應(yīng)商設(shè)備封裝： 416-PBGA（27x27）
包裝： 托盤
包括： 缺陷和警報(bào)檢測(cè)，驅(qū)動(dòng)器過流檢測(cè)和保護(hù)，LLOS 檢測(cè)，PRBSARB / IB 檢測(cè)和生成
產(chǎn)品目錄頁面： 1259 (CN2011-ZH PDF)
其它名稱： 800-1702
82P2816BBG
IDT82P2816
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Programming Information
90
February 6, 2009
RCF1 - Receive Configuration Register 1
Address: 00BH, 04BH, 08BH, 0CBH, 10BH, 14BH, 18BH, 1CBH, (CH1~CH8)
20BH, 24BH, 28BH, 2CBH, 30BH, 34BH, 38BH, 3CBH, (CH9~CH16)
7CBH (CH0)
Type: Read / Write
Default Value: 01H
Bit
Name
Description
7 - 5
RMF_DEF[2:0] These bits are valid only in Receive Single Rail NRZ Format mode and Receive Dual Rail Sliced mode. They determine the out-
put on the RMFn pin.
000: PRBS/ARB indication when the PRBS/ARB detection is switched to the receive path. Or reserved when the PRBS/ARB
detection is switched to the transmit path. (default)
001: LAIS indication.
010: XOR data of positive and negative sliced data.
011: Recovered clock (RCLK).
100: LEXZ indication.
101: LBPV indication.
110: LEXZ + LBPV indication.
111: LLOS indication.
4
RCK_ES
This bit selects the active edge of the RCLKn pin.
0: Rising edge. (default)
1: Falling edge.
3
RD_INV
This bit determines the active level on the RDn, RDPn and RDNn pins.
0: Active high. (default)
1: Active low.
2
R_CODE
This bit selects the line code rule for the receive path.
0: B8ZS (in T1/J1 mode) / HDB3 (in E1 mode). (default)
1: AMI.
1 - 0
R_MD[1:0]
These bits determines the receive system interface.
00: Receive Single Rail NRZ Format system interface. The data is output on RDn in NRZ format and a 1.544 MHz (in T1/J1
mode) or 2.048 MHz (in E1 mode) recovered clock is output on RCLKn.
01: Receive Dual Rail NRZ Format system interface. The data is output on RDPn and RDNn in NRZ format and a 1.544 MHz (in
T1/J1 mode) or 2.048 MHz (in E1 mode) recovered clock is output on RCLKn. (default)
10: Receive Dual Rail RZ Format system interface. The data is output on RDPn and RDNn in RZ format and a 1.544 MHz (in T1/
J1 mode) or 2.048 MHz (in E1 mode) recovered clock is output on RCLKn.
11: Receive Dual Rail Sliced system interface. The data is output on RDPn and RDNn in RZ format directly after passing through
the Slicer.
765
432
1
0
RMF_DEF2
RMF_DEF1
RMF_DEF0
RCK_ES
RD_INV
R_CODE
R_MD1
R_MD0
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參數(shù)描述
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