參數(shù)資料
型號(hào): IDT82P2816BBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 105/146頁
文件大小: 0K
描述: IC LINE INTERFACE UNIT 416-PBGA
標(biāo)準(zhǔn)包裝: 5
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 1
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 416-BGA
供應(yīng)商設(shè)備封裝: 416-PBGA(27x27)
包裝: 托盤
包括: 缺陷和警報(bào)檢測(cè),驅(qū)動(dòng)器過流檢測(cè)和保護(hù),LLOS 檢測(cè),PRBSARB / IB 檢測(cè)和生成
產(chǎn)品目錄頁面: 1259 (CN2011-ZH PDF)
其它名稱: 800-1702
82P2816BBG
IDT82P2816
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
61
February 6, 2009
3.6.3
MCLK, MASTER CLOCK INPUT
MCLK provides a stable reference timing for the IDT82P2816. MCLK
should be a clock with +/-32 ppm (in T1/J1 mode) or +/-50 ppm (in E1
mode) accuracy. The clock frequency of MCLK is set by pins
MCKSEL[3:0] and can be N x 1.544 MHz or N x 2.048 MHz with 1
≤ N ≤
8 (N is an integer number). Refer to MCKSEL[3:0] pin description for
details.
If there is a loss of MCLK (duty cycle is less than 30% for 10 s), the
device will enter power down. In this case, both the receive and transmit
circuits are turned off. The pins on the line interface will be in High-Z
state. The pins on receive system interface will be in High-Z state or in
low level, as selected by the RHZ bit (b6, RCF0,...). The input on the
transmit system interface is ignored and the output on the transmit
system interface will be in High-Z state. Refer to Section 3.2.7 Receiver
If MCLK recovers after loss of MCLK the device will be reset auto-
matically.
3.6.4
XCLK, INTERNAL REFERENCE CLOCK INPUT
XCLK is derived from MCLK. For the respective channel, it is 1.544
MHz in T1/J1 mode or 2.048 MHz in E1 mode. XCLK is used as select-
able reference clock for
pattern /AIS generation
RCLKn in LLOS
Loss of TCLKn to determine Transmit Output High-Z.
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