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| 型號： | IDT72T36135ML5BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/48頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO 1MX18 5NS 240BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 72T |
| 功能： | 異步，同步 |
| 存儲容量： | 18M（1M x 18） |
| 訪問時間： | 5ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BGA |
| 供應(yīng)商設(shè)備封裝： | 240-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T36135ML5BB |
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36135M 2.5V 18M-BIT TeraSync
36-BIT FIFO
524,288 x 36
15
FEBRUARY 04, 2009
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The
IDT72T36135Mhaveinternalregistersfortheseoffsets.Thereareeightdefault
offset values selectable during Master Reset. These offset values are shown
in Table 1. Offset values can also be programmed into the FIFO in one of two
ways; serial or parallel loading method. The selection of the loading method is
done using the
LD (Load) pin. During Master Reset, the state of the LD input
determineswhetherserialorparallelflagoffsetprogrammingisenabled.AHIGH
on
LDduringMasterResetselectsserialloadingofoffsetvalues.ALOWonLD
during Master Reset selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
For a more detailed description, see discussion that follows.
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter
Master Reset, regardless of whether serial or parallel programming has been
selected. Valid programming ranges are from 0 to D-1.
IDT72T36135M
*
LD
FSEL1
FSEL0
Offsets n,m
H
L
1,023
LH
L
511
L
H
255
L
127
LH
H
63
HH
L
31
HL
H
15
HH
H
7
*
LD
FSEL1
FSEL0
Program Mode
H
X
Serial(3)
L
X
Parallel(4)
*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
TABLE 1 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for
PAE[1:2].
2. m = full offset for
PAF[1:2].
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
6723 drw07
FF
PAF PAE
EF
HH
L
HH
L
H
HH
H
HL
H
LL
H
IDT72T36135M
0
1 to n
(1)
n + 1 to (524,288-(m+1))
524,288
Number of
Words in
FIFO
(524,288-m) to 524,287
IR
PAF PAE
OR
LH
L
H
LH
L
LH
H
L
LL
H
L
HL
H
L
IDT72T36135M
0
1 to n+1
n + 1 to (524,289-(m+1))
524,289
Number of
Words in
FIFO
(524,289-m) to 524,288
NOTE:
1. See Table 1 for values for n, m.
NOTE:
1. See Table 1 for values for n, m.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72T36135M can be configured during the Master Reset cycle with
eithersynchronousorasynchronoustimingfor
PAF[1:2]andPAE[1:2]flagsby
use of the PFM pin.
Ifsynchronous
PAF/PAE[1:2]configurationisselected(PFM,HIGHduring
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly,
PAE[1:2] is asserted and updated on the rising edge of
RCLK only and not WCLK. For detail timing diagrams, see Figure 22 for
synchronous
PAF[1:2]timingandFigure23forsynchronousPAE[1:2]timing.
Ifasynchronous
PAF/PAE[1:2]configurationisselected(PFM,LOWduring
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAF[1:2]isresettoHIGHontheLOW-to-HIGHtransitionofRCLK. Similarly,
PAE[1:2]isassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAE[1:2]
is reset to HIGH on the LOW-to-HIGH transition of WCLK. For detail timing
diagrams, see Figure 24 for asynchronous
PAF[1:2] timing and Figure 25 for
asynchronous
PAE[1:2]timing.
TABLE 2 — STATUS FLAGS FOR IDT
STANDARD MODE
TABLE 3 — STATUS FLAGS FOR FWFT
MODE
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| IDT72T36135ML5BBG | 功能描述:IC FIFO 1MX18 5NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36135ML6BB | 功能描述:IC FIFO 1MX18 6NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36135ML6BBI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 512KX36 ASYNC 240BGA |
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| IDT72T3645L4-4BBG | 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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