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參數(shù)資料
| 型號： | IDT72T36135ML5BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 15/48頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO 1MX18 5NS 240BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 72T |
| 功能： | 異步，同步 |
| 存儲容量： | 18M（1M x 18） |
| 訪問時間： | 5ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BGA |
| 供應(yīng)商設(shè)備封裝： | 240-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T36135ML5BB |
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36135M 2.5V 18M-BIT TeraSync
36-BIT FIFO
524,288 x 36
22
FEBRUARY 04, 2009
In FWFT mode, the Output Ready (
OR[1:2])functionisselected. OR[1:2]
goesLOWatthesametimethatthefirstwordwrittentoanemptyFIFOappears
validontheoutputs.
OR[1:2]staysLOWaftertheRCLKLOWtoHIGHtransition
thatshiftsthelastwordfromtheFIFOmemorytotheoutputs.
OR[1:2]goesHIGH
only with a true read (RCLK with
REN=LOW). Thepreviousdatastaysatthe
outputs,indicatingthelastwordwasread. Furtherdatareadsareinhibiteduntil
OR[1:2]goesLOWagain.SeeFigure14, ReadTiming(FWFTMode),forthe
relevanttiminginformation.
EF/OR[1:2] is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF[1:2] is a double register-buffered output. In
FWFT mode,
OR[1:2] is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF[1:2] )
TheProgrammableAlmost-Fullflag(
PAF[1:2])willgoLOWwhentheFIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS), PAF[1:2] will go LOW after (D - m) words are
written to the FIFO. The
PAF[1:2]willgoLOWafter(524,288-m)writesforthe
IDT72T36135M.Theoffset“m”isthefulloffsetvalue.Thedefaultsettingforthis
value is stated in the footnote of Table 2, Status Flags for IDT Standard Mode.
Please see Flagging section for external gating instructions of these flags.
In FWFT mode, the
PAF[1:2] will go LOW after(524,289-m) writes for the
IDT72T36135M,wheremisthefulloffsetvalue.Thedefaultsettingforthisvalue
is stated in Table 3, Status Flags for FWFT Mode.
See Figure 22, Synchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
Ifasynchronous
PAF[1:2]configurationisselected,thePAF[1:2]isasserted
LOW on the LOW-to-HIGH transition of the Write Clock (WCLK).
PAF[1:2]is
reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK). If
synchronous
PAF[1:2]configurationisselected,thePAF[1:2]isupdatedonthe
rising edge of WCLK. See Figure 24, Asynchronous Almost-Full Flag Timing
(IDT Standard and FWFT Mode).
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
write pointer to the ‘marked’ location. This differs from normal mode where this
flag is a comparison of the write pointer to the read pointer.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE[1:2])
The Programmable Almost-Empty flag (
PAE[1:2]) will go LOW when the
FIFOreachesthealmost-emptycondition.InIDTStandardmode,
PAE[1:2]will
go LOW when there are n words or less in the FIFO. The offset “n” is the empty
offsetvalue.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable 1.
Please see Flagging section for external gating instructions of these flags.
In FWFT mode, the
PAE[1:2] will go LOW when there are n+1 words or
less in the FIFO. The default setting for this value is stated in Table 1.
See Figure 23, Synchronous Programmable Almost-Empty Flag Timing
(IDT Standard and FWFT Mode), for the relevant timing information.
Ifasynchronous
PAE[1:2]configurationisselected,thePAE[1:2]isasserted
LOW on the LOW-to-HIGH transition of the Read Clock (RCLK).
PAE[1:2] is
reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK). If
synchronous
PAE[1:2]configurationisselected,thePAE[1:2]isupdatedonthe
rising edge of RCLK. See Figure 25, Asynchronous Programmable Almost-
Empty Flag Timing (IDT Standard and FWFT Mode).
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| IDT72T36135ML5BBG | 功能描述:IC FIFO 1MX18 5NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36135ML6BB | 功能描述:IC FIFO 1MX18 6NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36135ML6BBI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 512KX36 ASYNC 240BGA |
| IDT72T3645L4-4BB | 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72T3645L4-4BBG | 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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