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參數(shù)資料
| 型號(hào)： | IDT72T36135ML5BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 46/48頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO 1MX18 5NS 240BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 72T |
| 功能： | 異步，同步 |
| 存儲(chǔ)容量： | 18M（1M x 18） |
| 訪問時(shí)間： | 5ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BGA |
| 供應(yīng)商設(shè)備封裝： | 240-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T36135ML5BB |
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36135M 2.5V 18M-BIT TeraSync
36-BIT FIFO
524,288 x 36
7
FEBRUARY 04, 2009
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O TYPE
Description
RCLK/
Read Clock/
HSTL-LVTTL port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner.
RD
Read Strobe
INPUT
REN should be tied LOW.
RCS
Read Chip Select
HSTL-LVTTL
RCSprovidessynchronouscontrolofthereadportandoutputimpedanceofQn,synchronoustoRCLK.During
INPUT
a Master Reset or Partial Reset the
RCS input is don’t care, if OE is LOW the data outputs will be
Low-Impedance regardless of
RCS.
REN
Read Enable
HSTL-LVTTL If Synchronous operation of the read port has been selected,
REN enablesRCLK for reading data from the
INPUT
FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the
REN
input should be tied LOW.
RHSTL(1) Read Port HSTL
LVTTL
This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL inputs are required, this input
Select
INPUT
must be tied HIGH. Otherwise it should be tied LOW.
RT
Retransmit
HSTL-LVTTL
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF[1:2] flag to LOW
INPUT
(
OR[1:2]toHIGHinFWFTmode)anddoesn’tdisturbthewritepointer,programmingmethod,existingtiming
mode or programmable flag settings. If a mark has been set via the MARK input pin, then the read pointer will
jump to the ‘mark’ location.
SCLK
Serial Clock
HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that
INPUT
SEN is enabled.
SEN
Serial Enable
HSTL-LVTTL
SENenablesserialloadingofprogrammableflagoffsets.
INPUT
SHSTL
System HSTL
LVTTL
All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.
Select
INPUT
TCK(2)
JTAG Clock
HSTL-LVTTL Clock input for JTAG function. TMS and TDI are sampled on the rising edge of TCK. Data is output on
INPUT
TDO on the falling edge.
TRST(2)
JTAG Reset
HSTL-LVTTL
TRST is an asynchronous reset pin for the JTAG controller.
INPUT
TMS
JTAG Mode
HSTL-LVTTL TMS is a serial input pin. Bits are serially loaded on the rising edge of TCK, which selects 1 of 5 modes of
Select
INPUT
operation for the JTAG boundary scan.
TDI
Test Data Input
HSTL-LVTTL During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK.
INPUT
This is also the data for the Instruction Register, ID Register and Bypass Register.
TDO
TestDataOutput
HSTL-LVTTL During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK.
OUTPUT
This output is in High-Z except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
WEN
WriteEnable
HSTL-LVTTL When Synchronous operation of the write port has been selected,
WEN enables WCLK for writing data into
INPUT
theFIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the
WEN input should be tied LOW.
WCS
WriteChipSelect
HSTL-LVTTL This pin disables the write port data inputs when the device write port is configured for HSTL mode. This
INPUT
provides added power savings.
WCLK/
WriteClock/
HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by
WEN, the rising edge of
WR
WriteStrobe
INPUT
WCLK writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes
data into the FIFO on a rising edge in an Asynchronous manner, (
WEN should be tied to its active state).
WHSTL(1) Write Port HSTL
LVTTL
This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must
Select
INPUT
be tied HIGH. Otherwise it should be tied LOW.
Vcc
+2.5v Supply
Power
These are Vcc supply inputs and must be connected to the 2.5V supply rail.
GND
Ground Pin
GND
These are Ground pins an dmust be connected to the GND rail.
Vref
Reference
I
This is a Voltage Reference input and must be connected to a voltage level determined from the table,
Voltage
“Recommended DC Operating Conditions”. This provides the reference voltage when using HSTL class
inputs. If HSTL class inputs are not being used, this pin should be tied LOW.
VDDQ
O/P Rail Voltage
I
This pin should be tied to the desired voltage rail for providing power to the output drivers.
NOTES:
1. Inputs should not change state after Master Reset.
2. If the JTAG feature is not being used, TCK and
TRST should be tied LOW.
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| IDT72T36135ML5BBG | 功能描述:IC FIFO 1MX18 5NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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| IDT72T36135ML6BBI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 512KX36 ASYNC 240BGA |
| IDT72T3645L4-4BB | 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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