參數(shù)資料
型號(hào)： IDT72T36135ML5BB
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 16/48頁(yè)
文件大?。?/td> 0K
描述： IC FIFO 1MX18 5NS 240BGA
標(biāo)準(zhǔn)包裝： 1
系列： 72T
功能： 異步，同步
存儲(chǔ)容量： 18M（1M x 18）
訪問(wèn)時(shí)間： 5ns
電源電壓： 2.375 V ~ 2.625 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 240-BGA
供應(yīng)商設(shè)備封裝： 240-PBGA（19x19）
包裝： 托盤(pán)
其它名稱： 72T36135ML5BB
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36135M 2.5V 18M-BIT TeraSync
36-BIT FIFO
524,288 x 36
23
FEBRUARY 04, 2009
CONSIDERATIONS FOR READING FLAG OUTPUTS
On this device, there are two sets of flagging outputs for the empty flag (
EF1
&
EF2), full flag (FF1 & FF2), Programmable Almost Empty Flag (PAE1 &
PAE2),andProgrammableAlmostFullFlag(PAF1&PAF2)theusermustwork
withinordertobeabletocorrectlyreadthestatusofeachflag. Sincethisdevice
isamulti-chipmodule(MCM),bothdie’sflagsmustbereadaccordinglytoavoid
skewing problems between the two internal die.
To remedy this function, the user must tie together
FF1 & FF2, and EF1 &
EF2flagoutputstoanexternalgatefromaneighboringprogrammabledevice
such as an FPGA or PLD and read from the output of the logical gate. An OR
gate is used for FWFT mode and an AND gate is used for IDT mode. This must
be done to avoid timing skew problems between the two sets of flags. For the
PAE[1:2]andPAF[1:2]activelowoutputflags,theuserhastheoptiontoleave
the
PAE[1:2] and PAF[1:2]as is and use both pins at different programmable
water marks for measuring buffer status. Please see the section on Parallel
Programming Mode to understand how to program these two sets of flags as
different water marks in Functional Description section of the datasheet. This
gives added flexibility for queue management. Below is an example diagram
for how this is accomplished.
Figure 4. Output Flag Gating Considerations
PIN COMPATIBILITY WITH 9M TERASYNC (IDT72T36125) CONSIDER-
ATIONS
The IDT72T36135M can be a drop and replacement for the 9M TeraSync
(IDT72T36125) if specific pin changes are made to the 18M FIFO. Since the
18M TeraSync is a Multi-Chip Module (MCM), containing two 9M TeraSyncs
(IDT72T18125) in width expansion mode, certain functionality can not be
offered in the 18M TeraSync such as bus matching, single flag outputs and
interspersed parity. From these changes, the 18M FIFO has removed specific
inputssuchasIW,OW,BM,BE,IP,whilealsogaininganothersetofoutputflags
as specified in Considerations for Reading Flag Outputs which are
EF2,
FF2, PAE2, and PAF2.
Tomaintaindrop-inreplacementcompatibilityforthe18MTeraSync,thepin
changesonthepindiagramforthe18MTeraSyncFIFOfromthe9MTeraSync
FIFO have been identified, and listed in the table below.
TABLE 5 — PIN CHANGES BETWEEN 9M TERASYNC AND 18M TERASYNC
NOTES:
1. Internally, the 9M pins on the left side of the table will be tied to the GND or VDD plane, respectively in the 18M device.
2. Please see IDT72T36125 TeraSync FIFO datasheet for additional features listed.
6723 drw10
IDT72T36135M
EF1
EF2
FF1
FF2
PAE1
PAE2
PAF1
PAF2
GATE
(1)
GATE
(1)
AND
GATE
AND
GATE
OPTIONAL
EF
FF
PAE
PAF
9M TeraSync FIFO (IDT72T36125)
18M TeraSync FIFO (IDT72T36135M)
pins changed
new pins
BM
EF2
IP
PAE2
IW
NC (No Connect)
OW
NC (No Connect)
HF
PAF2
EREN
FF2
ERCLK
NC (No Connect)
BE
GND
NOTE:
1. An “OR” Gate is used for FWFT mode, and an “AND” Gate is used for IDT Standard mode.
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IDT72T36135ML6BB 功能描述:IC FIFO 1MX18 6NS 240BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T36135ML6BBI 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 512KX36 ASYNC 240BGA
IDT72T3645L4-4BB 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱:72271LA10PF
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