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參數(shù)資料
| 型號： | IDT72T36135ML5BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 45/48頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO 1MX18 5NS 240BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 72T |
| 功能： | 異步，同步 |
| 存儲容量： | 18M（1M x 18） |
| 訪問時間： | 5ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BGA |
| 供應(yīng)商設(shè)備封裝： | 240-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T36135ML5BB |
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36135M 2.5V 18M-BIT TeraSync
36-BIT FIFO
524,288 x 36
6
FEBRUARY 04, 2009
PIN DESCRIPTION
ASYR(1) Asynchronous
LVTTL
A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
Read Port
INPUT
willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.
ASYW(1) Asynchronous
LVTTL
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
WritePort
INPUT
will select Asynchronous operation.
D0–D35 DataInputs
HSTL-LVTTL Data inputs for a 36-bit bus.
INPUT
EF/OR Empty Flag/
HSTL-LVTTL In the IDT Standard mode, the
EF[1:2]functionisselected.EF[1:2]indicateswhetherornottheFIFOmemory
[1:2]
Output Ready
OUTPUT
is empty. In FWFT mode, the
OR[1:2]functionisselected.OR[1:2]indicateswhetherornotthereisvaliddata
available at the outputs. Please see Flagging section for external gating instructions of these flags.
FF/IR
Full Flag/
HSTL-LVTTL In the IDT Standard mode, the
FF[1:2]functionisselected.FF[1:2]indicateswhetherornottheFIFOmemory
[1:2]
Input Ready
OUTPUT
isfull.IntheFWFTmode,the
IR[1:2]functionisselected. IR[1:2]indicateswhetherornotthereisspaceavailable
for writing to the FIFO memory. Please see Flagging section for external gating instructions of
these flags.
FSEL0(1) Flag Select Bit 0
LVTTL
During Master Reset, this input along with FSEL1 and the
LD pin, will select the default offset values for the
INPUT
programmable flags
PAE[1:2] and PAF[1:2]. There are up to eight possible settings available.
FSEL1(1) Flag Select Bit 1
LVTTL
During Master Reset, this input along with FSEL0 and the
LD pin will select the default offset values for the
INPUT
programmable flags
PAE[1:2] and PAF[1:2]. There are up to eight possible settings available.
FWFT/
First Word Fall
HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
SI
Through/Serial In
INPUT
functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been
selected then the FIFO must be set-up in IDT Standard mode.
LD
Load
HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the
LD input along with FSEL0 and FSEL1,
INPUT
determinesoneofeightdefaultoffsetvaluesforthe
PAE[1:2]andPAF[1:2]flags,alongwiththemethodbywhich
these offset registers can be programmed, parallel or serial (see Table 1). After Master Reset, this pin enables
writing to and reading from the offset registers.
MARK
Mark for Retransmit HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit
INPUT
operation will reset the read pointer to this position.
MRS
Master Reset
HSTL-LVTTL
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master
INPUT
Reset, the FIFO is configured for either FWFT or IDT Standard mode,Synchronous/Asynchronous operation
of the read or write port, one of eight programmable flag default settings, serial or parallel programming of
the offset settings, zero latency timing mode, and synchronous versus asynchronous programmable flag
timingmodes.
OE
OutputEnable
HSTL-LVTTL
OE providesAsynchronousthree-statecontrolofthedataoutputs,Qn.DuringaMasterorPartialResetthe
INPUT
OE input is the only input that provide High-Impedance control of the data outputs.
PAE
Programmable
HSTL-LVTTL
PAE[1:2] goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the
[1:2]
Almost-EmptyFlag
OUTPUT
Empty Offset register.
PAE[1:2] goes HIGH if the number of words in the FIFO memory is greater than or
equal to offset n. Please see Flagging section for external gating instructions of these flags.
PAF
Programmable
HSTL-LVTTL
PAF[1:2]goesHIGHifthenumberoffreelocationsintheFIFOmemoryismorethanoffsetm,whichisstored
[1:2]
Almost-FullFlag
OUTPUT
in the Full Offset register.
PAF[1:2]goesLOWifthenumberoffreelocationsintheFIFOmemoryislessthan
or equal to m. Please see Flagging section for external gating instructions of these flags.
PFM(1)
Programmable
LVTTL
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on
Flag Mode
INPUT
PFM will select Synchronous Programmable flag timing mode.
PRS
PartialReset
HSTL-LVTTL
PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,
INPUT
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
Q0–Q35 DataOutputs
HSTL-LVTTL Data outputs for an 36-bit bus.
OUTPUT
RCLK/
Read Clock/
HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by
REN,therisingedgeofRCLK
RD
Read Stobe
INPUT
reads data from the FIFO memory and offsets from the programmable registers. If
LD is LOW, the values
loaded into the offset registers is output on a rising edge of RCLK.If Asynchronous operation of the read
Symbol
Name
I/O TYPE
Description
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| IDT72T36135ML5BBG | 功能描述:IC FIFO 1MX18 5NS 240BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36135ML6BB | 功能描述:IC FIFO 1MX18 6NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36135ML6BBI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 512KX36 ASYNC 240BGA |
| IDT72T3645L4-4BB | 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72T3645L4-4BBG | 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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