參數(shù)資料
型號: IDT71V65802S150BGG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 512K X 18 ZBT SRAM, 3.8 ns, PBGA119
封裝: 14 X 22 MM, GREEN, PLASTIC, BGA-119
文件頁數(shù): 23/26頁
文件大小: 970K
代理商: IDT71V65802S150BGG
6.42
6
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT
Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Pin Configuration - 512K x 18
100 TQFP Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Top View
100 TQFP
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. During production testing, the case temperature equals TA
.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol
Rating
Com mercial &
Industrial
Unit
VTERM
(2)
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
VTERM
(3,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD
V
VTERM
(4,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
V
VTERM
(5,6)
Terminal Voltage with
Respect to GND
-0.5 to VDDQ +0.5
V
TA(7)
Commercial
-0 to +70
oC
Industrial
-40 to +85
oC
TBIAS
Temperature
Under Bias
-55 to +125
oC
TSTG
Storage
Temperature
-55 to +125
oC
PT
Power Dissipation
2.0
W
IOUT
DC Output Current
50
mA
5303 tbl 06
Symbol
Parameter
(1)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 3dV
5
pF
CI/O
I/O Capacitance
VOUT = 3dV
7
pF
5303 tbl 07
100 99 98 97 96 95 94 93 92 91 90
87 86 85 84 83 82 81
89 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
C
E
1
C
E
2
N
C
N
C
B
W
2
B
W
1
C
E
2
V
D
V
S
C
LK
R
/W
C
E
N
O
E
A
D
V
/LD
N
C
(2
)
A
18
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D
N
U
(3
)
D
N
U
(3
)
D
N
U
(3
)
D
N
U
(3
)
LB
O
A
15
A
14
A
13
A
12
A
11
V
D
V
S
A
0
A
1
A
2
A
3
A
4
A
5
NC
VDDQ
VSS
NC
I/OP2
I/O15
I/O14
VSS
VDDQ
I/O13
I/O12
VSS
VDD
I/O11
I/O10
VDDQ
VSS
I/O9
I/O8
NC
VSS
VDDQ
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
VSS
VDDQ
NC
5303 drw 02a
VDD(1)
NC
VDD(1)
NC
A
16
A
17
NC
VDD(1)
A10
ZZ
,
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as
the input voltage is
≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective
JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows
these pins to be left unconnected, tied Low (VSS) or tied High (VDD).
Symbol
Parameter
(1)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 3dV
7
pF
CI/O
I/O Capacitance
VOUT = 3dV
7
pF
5303 tbl 07a
119 BGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
165 fBGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 3dV
TBD
pF
CI/O
I/O Capacitance
VOUT = 3dV
TBD
pF
5303 tbl 07b
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