參數(shù)資料
型號： IDT71V65802S150BGG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 512K X 18 ZBT SRAM, 3.8 ns, PBGA119
封裝： 14 X 22 MM, GREEN, PLASTIC, BGA-119
文件頁數(shù)： 12/26頁
文件大?。?/td> 970K
代理商： IDT71V65802S150BGG
6.42
2
IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT
Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Symbol
Pin Function
I/O
Active
Description
A0-A18
Address Inputs
I
N/A
Synchronous Address inputs. The address register is trig gered by a combination of the
rising edge of CLK, ADV/
LD low, CEN low, and true chip enables.
ADV/
LD
Advance / Load
I
N/A
ADV/
LD is a synchronous input that is used to load the internal registers with new address
and control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/
LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD
is sampled hig h then the internal burst counter is advanced for any burst that was in
progress. The external addresses are ignored when ADV/
LD is sampled high.
R/
W
Read / Write
I
N/A
R/
W signal is a synchronous input that identifies whether the current load cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
CEN
Clock Enable
I
LOW
Synchronous Clock Enable Input. When
CEN is sampled high, all other synchronous
inputs, including clock are ignored and outputs re main unchanged. The effect of
CEN
sampled high on the device outp uts is as if the low to hig h clock transition did not occur.
For normal operation,
CEN must be sampled low at rising edge of clock.
BW1-BW4
Individual Byte
Write Enables
I
LOW
Synchro nous byte write enables. Each 9-bit byte has its own active low byte write enable.
On load write cycles (When R/
W and ADV/LD are sampled low) the appropriate byte write
signal (
BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of
a burst write. Byte Write signals are ignored when R/
W is sampled high. The appropriate
byte(s) of data are written into the device two cycles later.
BW1-BW4 can all be tied low if
always doing write to the entire 36-bit word.
CE1, CE2
Chip Enables
I
LOW
Synchronous active low chip enable.
CE1 and CE2 are used with CE2 to enable the
IDT71V65602/5802. (
CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the
rising edge of clock, initiates a deselect cycle. The ZBTTM has a two cycle deselect, i.e.,
the data bus will tri-state two clock cycles after deselect is initiated.
CE2
Chip Enable
I
HIGH
Synchrono us active high chip enable. CE2 is used with
CE1 and CE2 to enable the chip.
CE2 has inverted po larity but otherwise identical to
CE1 and CE2.
CLK
Clock
I
N/A
This is the clock input to the IDT71V65602/5802. Except for
OE, all timing references for the
device are made with respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A
Synchro nous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW
Burst order selection input. When
LBO is high the Interleaved burst sequence is selected.
When
LBO is low the Linear burst sequence is selected. LBO is a static input and it must
not change during device operation.
OE
Output Enable
I
LOW
Asynchronous output enable.
OE must be low to read data from the IDT71V65602/5802.
When
OE is high the I/O pins are in a high-impedance state. OE does not need to be
actively controlled for read and write cycles. In normal operation,
OE can be tied low.
ZZ
Sleep Mode
I
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down
71V65602/5802 to the lowest p ower consumption level. Data retention is guaranteed in
Sleep Mode.
VDD
Power Supply
N/A
3.3V core power supply.
VDDQ
Power Supply
N/A
2.5V I/O Supply.
VSS
Ground
N/A
Ground.
5303 tbl 02
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
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IDT71V65802S150PF 功能描述:IC SRAM 9MBIT 150MHZ 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040
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