參數(shù)資料
型號: IDT71V416YL15PHI8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 256K X 16 STANDARD SRAM, 15 ns, PDSO44
封裝: 0.400 INCH, TSOP2-44
文件頁數(shù): 6/9頁
文件大小: 101K
代理商: IDT71V416YL15PHI8
6.42
6
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
ADDRESS
OE
CS
DATAOUT
6442 drw 07
(3)
DATA
VALID
tAA
tRC
tOE
tOLZ
BHE, BLE
(3)
tACS
(3)
tBLZ
tCLZ
(2)
tBE
(2)
tOH
tOHZ (3)
tCHZ (3)
tBHZ (3)
OUT
Timing Waveform of Read Cycle No. 2(1)
NOTES:
1. A write occurs during the overlap of a LOW
CS, LOW BHE or BLE, and a LOW WE.
2.
OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If
OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as
short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the
CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
NOTES:
1.
WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of
CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
ADDRESS
CS
DATAIN
6442 drw 0
(5)
DATAIN VALID
tWC
tAS
tWHZ
(2)
tCW
tCHZ
tOW
tWR
WE
tAW
DATAOUT
tDW
tDH
PREVIOUS DATA VALID
DATA VALID
BHE, BLE
tBW
tWP
(5)
tBHZ
(3)
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