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參數(shù)資料
| 型號(hào)： | ICSSSTUA32866BHLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 5.50 X 13.50 MM, LEAD FREE, MO-205, LFBGA-96 |
| 文件頁數(shù)： | 8/27頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ICSSSTUA32866BHLFT |
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16
ICSSSTUA32866B
1054A—01/28/05
2. Device standard (cont'd)
Figure 15 — Timing diagram for the second SSTU32866 (1:2 register-B configration) device used in
pair; C0 = 1, C1 = 1; RST# switches from L to H
After
switched fro
low to high, al data and PAR_IN inputs signals must be se and held lo
for a minimum time of tACT
max, to avoid false error
PAR_IN is driven from PPO of the first SSTU32866 device
§
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse.
CK
D1D14
RST#
tsu
tpd
CK to PPO
th
tsu
th
tpdm , t pdmss
CK to Q
DCS#
CSR#
CK#
Q1Q14
PAR_IN
n
n + 1
n + 2
PPO
(not used)
n + 3
n + 4
tPHL
CK to QERR#
QERR# §
tPHL , t PLH
CK to QERR#
tact
H, L, or X
H or L
Data to QERR#
Latency
RST#
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