參數(shù)資料
型號(hào): ICSSSTUA32866BHLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 鎖存器
英文描述: SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96
封裝: 5.50 X 13.50 MM, LEAD FREE, MO-205, LFBGA-96
文件頁數(shù): 6/27頁
文件大?。?/td> 307K
代理商: ICSSSTUA32866BHLFT
14
ICSSSTUA32866B
1054A—01/28/05
2. Device standard (cont'd)
Figure 13 — Timing diagram for the firs SSTU32866 (1:2 register-A configration) device used in
pair; C0 = 0, C1 = 1; RST# bein held high
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+1 clock pulse, and it will be valid on
the n+2 clock pulse. If an error occurs and the QERR# output is driven low, it stays latched low for a minimum of two clock cycles or
until RST# is driven low.
CK
D1D14
RST#
tsu
tpd
CK to PPO
th
tsu
th
tpdm , t pdmss
CK to Q
DCS#
CSR#
CK#
Q1Q14
PAR_IN
n
n + 1
n + 2
PPO
n + 3
n + 4
QERR#
(not used)
tPHL or t PLH
CK to QERR#
Unknown input
event
H or L
Output signal is dependent on
the prior unknown input event
Data to QERR#
Latency
Data to PPO
Latency
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